Hysteresis and Eddy Current Loss

When a magnetic material (iron core) is subjected to an alternating magnetic field, energy is dissipated in the form of heat. This total energy loss in the core is called core loss or iron loss, and it has two components:

1. Hysteresis Loss

When the iron core is magnetised and demagnetised alternately by an alternating current, the magnetic domains in the iron are forced to rotate and reorient themselves in the direction of the applied field in every half cycle. The domain walls have to overcome internal friction during this reorientation. The work done against this internal friction appears as heat in the core. This loss of energy is called hysteresis loss.

It is given by Steinmetz's formula:

$P_h = \eta \, B_{max}^{1.6} \, f \, V \quad \text{(watts)}$

where $\eta$ = hysteresis coefficient, $B_{max}$ = maximum flux density, $f$ = frequency, $V$ = volume of the core.

2. Eddy Current Loss

The alternating flux in the core induces circulating currents (called eddy currents) in the body of the iron core itself, in planes perpendicular to the flux. These currents flow through the resistance of the iron and dissipate energy as heat. This is called eddy current loss.

It is reduced by using laminated sheets (thin sheets insulated from each other) instead of a solid core. The loss is given by:

$P_e = k \, B_{max}^{2} \, f^{2} \, t^{2} \, V \quad \text{(watts)}$

where $t$ = thickness of each lamination and $k$ is a constant.

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Hysteresis Loop

When a ferromagnetic material is taken through a complete cycle of magnetisation and demagnetisation, the graph of flux density $B$ against magnetising force $H$ traces a closed loop called the hysteresis loop (B–H curve).

Explanation of the loop:

1. O → A (Initial magnetisation): Starting from the unmagnetised state at O, as $H$ increases, $B$ increases along OA and reaches saturation at A.
2. A → B (Remanence): When $H$ is reduced to zero, $B$ does not fall to zero but retains a value OB, called the residual flux density or remanence.
3. B → C (Coercivity): To reduce $B$ to zero, a reverse field OC must be applied. This value OC is called the coercive force.
4. C → D → E: On increasing the reverse field, saturation is reached at D in the opposite direction. Reducing $H$ to zero again leaves a residual flux in the reverse direction, and a forward field OE is needed to bring $B$ to zero.
5. E → A: The cycle is completed, giving the closed loop ABCDEF.

The area enclosed by the hysteresis loop represents the energy lost per unit volume of the material per cycle. A material with a narrow loop (soft iron) has small hysteresis loss, while a material with a wide loop (steel) has large hysteresis loss.

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Derivation of Energy Stored and Returned per Cycle

Consider a ring (toroid) of iron of mean length $l$, area of cross-section $A$, and volume $V = A\,l$, wound with $N$ turns carrying current $I$.

The magnetising force is

$H = \frac{NI}{l} \quad \Rightarrow \quad I = \frac{Hl}{N}$

The flux linked with the winding is

$\Phi = BA \quad \Rightarrow \quad \text{flux linkage} = NBA$

The instantaneous electrical energy supplied to the coil in time $dt$ is

$dW = (\text{induced emf}) \times I \, dt = N\frac{d\Phi}{dt} \cdot I \, dt = N \, I \, d\Phi$

Substituting $I = \dfrac{Hl}{N}$ and $d\Phi = A \, dB$:

$dW = N \cdot \frac{Hl}{N} \cdot A \, dB = A \, l \, H \, dB = V \, H \, dB$

Therefore the energy supplied per unit volume for a small change $dB$ is

$dw = H \, dB$

Energy stored (during magnetisation): As $H$ increases from 0 to $H_{max}$, the energy stored per unit volume is the area under the rising curve:

$w_{\text{stored}} = \int_{0}^{B_{max}} H \, dB$

Energy returned (during demagnetisation): As $H$ decreases from $H_{max}$ back to 0, the energy returned per unit volume is the area under the falling curve:

$w_{\text{returned}} = \int_{B_{max}}^{0} H \, dB \quad \text{(taken with sign)}$

Net energy lost per cycle per unit volume: The difference between energy stored and energy returned equals the area enclosed by the hysteresis loop:

$w_{\text{loss}} = \oint H \, dB = \text{area of the hysteresis loop}$

For the complete cycle $0 \leq t \leq 2\pi$ (one full a.c. cycle), the total hysteresis energy loss in the core of volume $V$ is

$\boxed{W_h = V \oint H \, dB = V \times (\text{area enclosed by the B–H loop})}$

This energy is dissipated as heat in the iron core in every cycle. Hence the hysteresis power loss is

$P_h = f \, W_h = f \, V \oint H \, dB$

which agrees with Steinmetz's empirical formula $P_h = \eta B_{max}^{1.6} f V$.

Load curve. A load curve is a graph plotted with time along the x-axis (hours of the day, or months of the year) and the load (demand) in kW or MW along the y-axis. It shows how the system load varies with time. The area under the curve gives the energy consumed in kWh. A daily load curve covers 24 hours; an annual load curve covers 12 months. The peak of the curve gives the maximum demand.

Load duration curve. A load duration curve is obtained by rearranging the load values of a load curve in descending order of magnitude, so that the x-axis represents the duration (number of hours or percentage of time) for which a given load is equalled or exceeded. The area under it is the same as that under the load curve, i.e. the total energy. It is used to decide the base load, peak load and the sequence in which different plants should be operated.

Mass curve. A mass curve (integrated load curve) is a plot of cumulative energy (kWh) against time. The slope at any point gives the load at that instant. The difference in ordinates between two points gives the energy consumed in that interval. It is used to determine the capacity of storage reservoirs and to study the energy demand pattern.

Significance in generation planning.

Load factor = average load / maximum demand = (energy in kWh) / (maximum demand × hours). A high load factor means the plant capacity is used steadily and the fixed cost per unit is low; it decides the size of plant and the tariff structure.

Plant factor (capacity factor) = average load / rated capacity of plant = actual energy generated / (plant capacity × hours). It indicates how fully the installed capacity is utilised and helps in selecting the type and size of generating units.

Diversity factor = sum of individual maximum demands / maximum demand of the system. Since it is always greater than 1, it shows that the system peak is less than the sum of consumer peaks. A high diversity factor reduces the required installed capacity and hence the capital cost, so it is a key factor in deciding the total generation capacity to be installed.

Boost Converter (Step-Up DC–DC Converter)

1. Working Principle

A boost converter is a switched-mode DC–DC converter that produces an output voltage greater than its input voltage. It uses only two energy-storage/reactive elements — an inductor $L$ and a capacitor $C$ — plus a controlled switch $S$ (usually a MOSFET) and a diode $D$.

The operation depends on the property of an inductor to oppose changes in current. The switch is turned ON and OFF at a high frequency (tens of kHz to a few hundred kHz) with a duty cycle $D$. Two modes occur in each switching cycle:

Mode 1 — Switch ON ($0 \le t \le DT$): The switch short-circuits the inductor to the source. The diode is reverse-biased, so the load is isolated and is fed only by the capacitor. The inductor current rises linearly, storing energy in its magnetic field:

$V_L = V_{in} = L\frac{di_L}{dt}$

Mode 2 — Switch OFF ($DT \le t \le T$): The switch opens. The inductor opposes the sudden current change and reverses its voltage, so the source voltage plus the induced EMF now forward-bias the diode. Energy flows to the load and also recharges the capacitor. The inductor current falls linearly:

$V_L = V_{in} - V_o = L\frac{di_L}{dt}$

2. Circuit Layout

        L                    D
   +───████████───┬──────────▶|────────┬───────┬─── V_o (+)
   |              |                    |       |
  V_in           [S]  (MOSFET)         |      === C
   |              |                    |       |
   └──────────────┴────────────────────┴───────┴─── V_o (−)

• $L$ — inductor, stores energy during ON time
• $S$ — controlled switch (MOSFET), driven by PWM gate signal
• $D$ — diode, conducts only during OFF time
• $C$ — output capacitor, smooths the output voltage
• $R$ — load (here, the inverter/grid interface)

3. Derivation of Output Voltage and Duty Cycle

Volt–second balance on the inductor. In steady state, the average voltage across an inductor over one complete cycle is zero:

$\int_0^{DT} V_L\,dt + \int_{DT}^{T} V_L\,dt = 0$

Substituting the two modes:

$V_{in}(DT) + (V_{in} - V_o)(1-D)T = 0$

Dividing by $T$:

$V_{in}D + V_{in}(1-D) - V_o(1-D) = 0$

$V_{in} - V_o(1-D) = 0$

$\boxed{V_o = \frac{V_{in}}{1-D}}$

Duty cycle:

$\boxed{D = 1 - \frac{V_{in}}{V_o}}$

Since $0 < D < 1$, the factor $\dfrac{1}{1-D} > 1$, confirming step-up action. As $D \to 1$, $V_o \to \infty$ ideally; in practice, losses and parasitic resistances limit the achievable gain to about 4–5 times $V_{in}$.

Ideal current relation (from power balance, $V_{in}I_{in} = V_oI_o$):

$\frac{I_o}{I_{in}} = 1 - D$

4. Suitability for Interfacing a Solar PV System with the Grid

Verdict: A boost converter is technically well suited — and in fact is the standard choice — for the DC–DC stage between a PV array and a grid-connected inverter.

Technical reasoning:

1. Voltage matching. A PV module's maximum-power-point voltage ($V_{mp}$) is typically 30–40 V per module, and even a series string may give only 200–400 V DC. A single-phase grid inverter needs a DC-link of about 350–400 V (peak of 230 V rms) and a three-phase inverter about 550–650 V. The boost converter steps the lower PV voltage up to this required DC-link level, which a buck converter cannot do.

2. MPPT compatibility. The PV array must always be operated at its maximum power point, which shifts with irradiance and temperature. The boost converter's duty cycle $D$ provides a continuous control variable: by adjusting $D$, the input impedance seen by the array is varied so that the array voltage is forced to $V_{mp}$. This is the basis of nearly all MPPT algorithms (P&O, incremental conductance).

3. Continuous input current. The inductor sits directly at the input, so the PV current drawn is continuous and only mildly rippled. This suits the essentially DC nature of a PV source and reduces stress on the panels, unlike a buck converter whose input current is pulsating.

4. Unidirectional power flow. The diode gives inherent one-way conduction, matching the unidirectional nature of PV generation and preventing reverse current into the array at night.

5. High efficiency and simple topology. With a single switch and diode, efficiencies of 95–98 % are achievable, and the single control variable $D$ simplifies the control loop.

Limitations to note: The boost converter cannot step down, so it needs $V_{in} < V_o$ at all times; on very hot days $V_{mp}$ may fall close to the DC-link voltage and the converter loses controllability. Also, the output current is pulsating (handled by the DC-link capacitor), and the right-half-plane zero in its control-to-output transfer function makes the voltage loop slower — so MPPT is normally implemented on the input side. These are design issues, not fundamental barriers.

Conclusion: The boost converter is the standard, technically justified choice for the PV-to-grid DC–DC interface, because it steps up the low PV voltage to the inverter DC-link level while simultaneously providing the duty-cycle control needed for maximum power point tracking.

Factors Influencing the Choice of Transmission Voltage

The transmission voltage for a new line is fixed at the planning stage, since it determines conductor size, insulation, tower height, right-of-way width and the cost of terminal equipment. The main factors are:

1. Amount of power to be transmitted Power capacity rises roughly with the square of voltage: $P \propto V^2$ A line that must carry 500 MW cannot be built economically at 66 kV; it needs 220 kV or above. Higher voltage reduces current for the same power, hence smaller conductors and lower $I^2R$ loss.

2. Distance of transmission Line losses and voltage drop are proportional to distance. For long distances the saving in conductor copper and energy loss outweighs the higher cost of insulators, towers and transformers. Power transfer capability is also limited by the surge impedance loading (SIL): $\text{SIL} = \frac{V^2}{Z_c}$ so a higher voltage raises the natural loading of the line.

3. Cost economics (capital vs. operating cost) A higher voltage means costlier transformers, switchgear, insulators and taller towers (higher capital cost), but cheaper conductors and lower losses (lower running cost). The voltage chosen is the one giving minimum total annual cost over the life of the project.

4. Voltage drop and regulation limits Voltage regulation must stay within permissible limits (about ±6% to ±10%). A long line at low voltage would need impractically large conductors to meet this, so voltage is raised.

5. Corona loss and radio interference Corona loss and interference increase with voltage but fall sharply with conductor diameter. Above about 220 kV, bundled conductors (2, 4 or more sub-conductors per phase) are used to keep the surface voltage gradient below the corona limit. This is why EHV lines use bundle conductors.

6. Insulation and clearance requirements Higher voltage needs larger air clearance, longer insulator strings and wider right-of-way. In hilly terrain (as in Nepal) this sharply raises tower and land cost, which discourages very high voltages for short lines.

7. Standardisation and system interconnection Voltages must match the existing grid so that lines can be interconnected and spares standardised. Nepal uses 66 kV, 132 kV, 220 kV and 400 kV as standard levels.

8. Short-circuit capacity and stability Higher voltage raises fault levels and demands heavier switchgear, but improves transient stability by reducing transfer reactance between generating stations.

Examples at Different Voltage Levels

For instance, the Kaligandaki–Kathmandu corridor at 132 kV suits a 100 MW transfer over about 150 km, while the 400 kV Dhalkebar–Muzzafarpur cross-border link is justified because it moves 1000 MW class power over a long distance and must match the Indian grid voltage.

ABCD Parameters as a Transmission Line Model

A transmission line is a two-port network. Taking sending end quantities (voltage $V_S$, current $I_S$) and receiving end quantities ($V_R$, $I_R$), the network is described by:

$\begin{bmatrix} V_S \\ I_S \end{bmatrix} = \begin{bmatrix} A & B \\ C & D \end{bmatrix} \begin{bmatrix} V_R \\ I_R \end{bmatrix}$

where

$V_S = A V_R + B I_R, \qquad I_S = C V_R + D I_R$

The parameters are complex constants determined by the line's series impedance $Z$ and shunt admittance $Y$ per unit length, and its length $l$:

• Short line ($l < 80$ km): $A = D = 1$, $B = Z$, $C = 0$
• Medium line (nominal-$\pi$): $A = D = 1 + \frac{YZ}{2}$, $B = Z$, $C = Y\left(1 + \frac{YZ}{4}\right)$
• Long line: $A = D = \cosh \gamma l$, $B = Z_c \sinh \gamma l$, $C = \frac{\sinh \gamma l}{Z_c}$, where $\gamma = \sqrt{ZY}$ and $Z_c = \sqrt{Z/Y}$

For a symmetrical (reciprocal) network, $AD - BC = 1$; for a symmetrical line also $A = D$. These relations let any two parameters be found from the other two.

Advantages of ABCD Parameters over Other Models

1. Cascade (series) connection is simple. For two lines in cascade, the overall matrix is just the product of the individual matrices: $\begin{bmatrix} A & B \\ C & D \end{bmatrix} = \begin{bmatrix} A_1 & B_1 \\ C_1 & D_1 \end{bmatrix} \begin{bmatrix} A_2 & B_2 \\ C_2 & D_2 \end{bmatrix}$ This is far easier than combining separate equivalent-$\pi$ or equivalent-$T$ circuits.

2. General and exact. The same formulation covers short, medium and long lines; the long-line (distributed parameter) case is handled exactly, whereas lumped models are approximations valid only at low frequency and short length.

3. Terminal quantities only. Only sending and receiving end voltages and currents appear, so the model is ideal for power system studies, load flow and fault analysis without solving the line internally.

4. Easy computation of regulation and efficiency. With $A$, $B$, $C$, $D$ known:

   • Voltage regulation $= \dfrac{|V_{R(\text{no load})}| - |V_R|}{|V_R|}$
   • Efficiency $= \dfrac{|V_R||I_R|\cos\phi_R}{|V_S||I_S|\cos\phi_S}$
   • Sending end power circle diagram and receiving end power limits follow directly.

5. Symmetry and reciprocity checks. The conditions $A = D$ and $AD - BC = 1$ give a quick verification of the model and of physical line symmetry, which lumped models do not provide so directly.

6. Compact representation. A whole line, however long, is represented by only four complex numbers, which is convenient for computer-based network solutions and for building the bus admittance matrix.

Thus the ABCD (transmission) parameters give a general, exact and easily cascadable two-port representation of a transmission line, making them the standard tool for analysing power transfer, regulation and efficiency at any voltage level.

Importance of Load Flow Analysis in Power System Studies

Load flow (power flow) analysis is the backbone of power system planning and operation. Its importance includes:

1. Steady-state operating condition: It determines the voltage magnitude and phase angle at every bus, and the real and reactive power flows on every line, for a given set of generation and load conditions.
2. Voltage profile and reactive power management — identifies buses with unacceptable voltage, guiding transformer tap settings and reactive compensation (capacitors, SVCs).
3. Line loading and thermal check — reveals overloaded lines/transformers so that reinforcement or rescheduling can be done.
4. Loss evaluation — computes I²R transmission losses, useful for economic dispatch and loss minimization.
5. Planning and expansion — used to test new lines, substations and generation additions before investment.
6. Contingency and security analysis — base case for outage studies (N-1), short-circuit and stability studies.
7. Setting the base case for transient/voltage stability and state estimation.

Classification of Buses

Each bus has four quantities: P, Q, |V|, θ. Two are specified and two are unknowns. On this basis buses are classified as:

If a PV bus hits its Q limit, it is converted to a PQ bus (and vice-versa).

Common Algorithms

1. Gauss–Seidel method

• Principle: Iteratively solve each bus equation using the latest available values; Y-bus based.
• Advantages: Simple, needs little memory, easy to program.
• Limitations: Very slow convergence (linear), number of iterations rises sharply with size; poor for ill-conditioned systems.

2. Newton–Raphson (NR) method

• Principle: Solve the nonlinear power equations using the Jacobian matrix; quadratic convergence.
• Advantages: Very fast convergence (3–5 iterations regardless of size), accurate, handles ill-conditioning well.
• Limitations: Needs Jacobian formation and inversion each iteration → large memory and computation per iteration; sensitive to poor initial guess.

3. Fast Decoupled Load Flow (FDLF)

• Principle: Exploits the weak coupling between P–θ and Q–|V| (since R ≪ X); uses constant, pre-factorised B′ and B″ matrices.
• Advantages: Very fast per iteration, low memory, ideal for large systems and real-time/online use.
• Limitations: Valid only for high X/R (transmission) networks; diverges for heavily loaded or distribution-type systems; approximate.

4. DC load flow — linearised (θ only, losses neglected); used for fast contingency screening.

Conclusion: NR/FDLF are the workhorses of modern load flow; Gauss–Seidel is only of academic/small-system value.

Disconnecting Switch (DS) — Operation and Types

What is a Disconnecting Switch?

A disconnecting switch (DS), also called an isolator or isolating switch, is an off-load switching device used in a substation to isolate a circuit or piece of equipment from the live supply for maintenance and safety. It is not designed to make or break load current or fault current — it is operated only after the associated circuit breaker has already interrupted the current. Its function is to provide a visible air gap so that maintenance staff can work safely.

How it Operates

• The DS is opened or closed only when no current is flowing in the circuit (the circuit breaker is opened first).
• It is operated manually (hand crank/lever) or by a motor drive, remotely or locally.
• When closed, the moving blade contacts the fixed jaw and completes the circuit; when opened, a clear air gap appears between the blade and the jaw.
• Interlocks are provided so that the DS cannot be opened while the circuit breaker is closed, and the circuit breaker cannot be closed while the DS is open.
• The air gap provides visible isolation and withstands the system voltage to ground and across the gap.

DS With and Without Earth Switch

Where used: DS with earth switch is used on transmission line bays, transformer HV terminals and busbars where the isolated section must be positively earthed before work. DS without earth switch is used where earthing is done by a separate earthing device or where the section is earthed through another path.

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Differential Protection System

Principle

Differential protection works on Kirchhoff's current law: for a healthy transformer, the current entering the protected zone equals the current leaving it (after accounting for the transformer ratio). A current transformer (CT) is mounted on each side of the transformer, and the secondary currents are compared in a differential relay. Under normal conditions and external faults, the currents balance and no current flows in the relay operating coil. For an internal fault, the balance is disturbed and the difference current operates the relay to trip the circuit breakers.

Schematic Diagram — Step-up Transformer Protection

        CT1 (HV side)                         CT2 (LV side)
   ┌──────────┐                          ┌──────────┐
   │  CB1     │                          │  CB2     │
   │          │                          │          │
   │   ┌──────┴──────┐            ┌──────┴──────┐   │
   │   │             │            │             │   │
   │   │   POWER     │            │             │   │
   │   │ TRANSFORMER │            │             │   │
   │   │  (Step-up)  │            │             │   │
   │   │             │            │             │   │
   │   └──────┬──────┘            └──────┬──────┘   │
   │          │                          │          │
   └──────────┘                          └──────────┘
        │                                      │
        │  I1                                  │  I2
        ▼                                      ▼
   ┌─────────┐                           ┌─────────┐
   │  CT1    │                           │  CT2    │
   └────┬────┘                           └────┬────┘
        │                                      │
        │        ┌───────────────┐             │
        └───────►│  DIFFERENTIAL │◄────────────┘
                 │    RELAY      │
                 │   (87T)       │
                 └───────┬───────┘
                         │ Trip signal
                         ▼
                 ┌───────────────┐
                 │  TRIP CIRCUIT │
                 └───────┬───────┘
                         │
              ┌──────────┴──────────┐
              ▼                     ▼
         ┌─────────┐           ┌─────────┐
         │  CB1    │           │  CB2    │
         │ (HV)    │           │ (LV)    │
         └─────────┘           └─────────┘

Functioning

1. Normal operation: The secondary currents from CT1 and CT2 are equal and opposite in the relay circuit, so the net operating current is zero. The relay does not operate.
2. External fault: Both CTs see the same fault current (referred through the ratio), so the currents still balance and the relay remains stable. Biasing/restraint is applied to prevent maloperation due to CT errors.
3. Internal fault: The current entering the transformer no longer equals the current leaving it. The difference current flows through the relay operating coil and exceeds the setting, so the relay (87T) operates.
4. Tripping: The relay sends a trip signal to the trip circuit, which trips both the HV and LV circuit breakers, isolating the faulty transformer from the system.

Special Features for Transformer Differential Protection

• CT ratio matching: Since the HV and LV currents differ, CT ratios are chosen so secondary currents match.
• Vector group compensation: Phase shift between HV and LV (e.g., Dyn11) is compensated by connecting CT secondaries in delta/star.
• Zero-sequence filtering: Prevents maloperation during external earth faults.
• Harmonic restraint: Second-harmonic restraint blocks tripping during magnetising inrush current.
• Percentage bias: Provides stability for through faults while remaining sensitive to internal faults.

This makes differential protection the main and fastest protection for transformers, operating in a few cycles for internal faults.

Fire Fighting Techniques and Equipment for Electricity Fire Hazards

Nature of electrical fires: Electrical fires are Class C fires (energised electrical equipment) and often involve Class A (solid) or Class B (flammable liquid) materials nearby. The key principle is that electricity must be cut off before attacking the fire, otherwise the extinguishing agent and the operator may conduct current.

Fire Fighting Techniques

1. De-energise the circuit first — Switch off the main breaker/isolator, or trip the upstream protective device. Only after isolation should the fire be fought as an ordinary fire.
2. Use non-conducting extinguishing agents — CO₂, dry chemical powder (DCP/ABC), or clean agents (FM-200, Novec 1230). Never use water or foam on live equipment.
3. Smothering / blanketing — CO₂ displaces oxygen and cools the surface without leaving residue, ideal for panels, switchgear and computers.
4. Cooling — Once de-energised, water spray or foam may be used to cool surrounding Class A/B materials.
5. Starving (fuel removal) — Remove nearby combustible materials and isolate the affected section to prevent spread.
6. Evacuation and alarm — Raise the alarm, evacuate personnel, call the fire brigade; use the PASS technique (Pull, Aim, Squeeze, Sweep) for portable extinguishers.
7. Do not open the equipment while burning — Opening a panel admits oxygen and can cause arc flash/backdraft.

Fire Fighting Equipment

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Earthing (Grounding)

Concept: Earthing connects the non-current-carrying metallic parts of an installation (enclosure, frame, neutral point) to the general mass of earth through a low-resistance path, so that fault current flows to earth and the protective device operates.

Purpose:

• Provides a low-resistance path for fault current → fast operation of fuse/MCB/ELCB.
• Limits touch and step potential to safe values, protecting personnel.
• Protects equipment from lightning and surges.
• Maintains the neutral point at earth potential in star-connected systems.

Types:

• Pipe earthing — galvanised iron pipe buried vertically with charcoal and salt.
• Plate earthing — copper or GI plate buried in layers of charcoal and salt.
• Rod earthing — copper rod driven into the ground.
• Strip/water-main earthing — for large installations.

Desirable earth resistance: Generally ≤ 1 Ω for substations and ≤ 5 Ω for domestic installations (values vary with the applicable standard).

Formula: $R = \frac{\rho}{2\pi L}\left(\ln\frac{4L}{a}-1\right)$ where $\rho$ = soil resistivity, $L$ = electrode length, $a$ = electrode radius.

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Shielding

Concept: Shielding encloses conductors, equipment or cables with a conductive (usually metallic) barrier connected to earth, to block electromagnetic interference (EMI) and to control electric field stress.

Types and techniques:

1. Electrostatic shielding — A conductive enclosure (Faraday cage) around equipment prevents external electric fields from inducing voltages; it also prevents internal fields from escaping.
2. Electromagnetic shielding — Metallic braid, foil or conduit around cables absorbs/reflects EM waves; used in instrumentation and communication cables.
3. Cable shielding — Metallic sheath/braid over insulated conductors, earthed at one or both ends, reduces induced voltages and interference.
4. Grading shields in HV cables — Conductive/dielectric screens around the conductor equalise electric stress and prevent insulation breakdown.
5. Shielded rooms / enclosures — For sensitive control rooms, data centres and hospitals.

Earthing of shields: The shield must be bonded to the earthing system; otherwise it acts as an antenna and worsens interference. For long cables, shields are commonly earthed at both ends to limit induced voltage and provide a low-impedance return path for interference currents — but this can create circulating currents if the two earth points differ in potential. Where circulating currents are a concern (e.g. instrumentation cables), single-point (source-end) earthing is preferred, accepting some induced voltage. The choice is thus a trade-off between induced-voltage control and ground-loop current avoidance.

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Conclusion: For electrical fires, the correct sequence is isolate → alarm → extinguish with a non-conducting agent. Earthing ensures fault current returns safely and protective devices operate, while shielding suppresses electromagnetic interference and controls dielectric stress — together they form the backbone of electrical safety.

Digital Signal Processing (DSP) and Signal Transmission/Reception

DSP is the technique of processing signals (speech, audio, video, radar, data) after converting them into digital form — a sequence of numbers — using algorithms implemented in hardware (DSP chips, FPGA) or software. Because the signal is represented as numbers, it can be manipulated mathematically with high precision, stored, repeated and transmitted without degradation.

Block Diagram of a DSP System

        ┌──────────────┐   ┌─────┐   ┌───────────────┐   ┌─────┐   ┌──────────────┐
Analog  │ Anti-alias   │   │     │   │  DSP Core     │   │     │   │ Reconstruct  │  Analog
Input ─►│ (Low-pass)   │──►│ ADC │──►│ (Algorithm /  │──►│ DAC │──►│ (Smoothing)  │─► Output
Signal  │  Filter      │   │     │   │  FIR/IIR, FFT)│   │     │   │  Filter      │
        └──────────────┘   └─────┘   └───────┬───────┘   └─────┘   └──────────────┘
                                            │
                                     ┌──────┴──────┐
                                     │  Memory /   │
                                     │ Coefficient │
                                     │   Storage   │
                                     └─────────────┘

Stages: Anti-alias filter limits bandwidth → ADC samples and quantises → DSP core executes the algorithm (filtering, modulation, coding, compression) → DAC converts back → reconstruction filter removes sampling images.

How DSP Improves Transmission

1. Digital modulation — QPSK, QAM, OFDM, spread spectrum are generated numerically, giving high spectral efficiency and better bandwidth utilisation.
2. Source coding (compression) — speech (LPC, CELP) and image (JPEG) data are compressed so more channels fit in the same bandwidth.
3. Channel coding — convolutional, Reed–Solomon and turbo codes add redundancy for forward error correction (FEC).
4. Adaptive equalisation and pre-distortion — the transmitter pre-compensates channel distortion, so the received eye diagram stays open.
5. Error-free regeneration — digital repeaters regenerate clean pulses instead of amplifying noise as analog repeaters do.
6. Encryption and multiplexing — secure and spectrally efficient transmission (TDM, FDM, CDMA) is easily implemented.

How DSP Improves Reception

1. Digital filtering — sharp-cutoff FIR/IIR filters separate the wanted band from adjacent channels and noise.
2. Coherent demodulation and synchronisation — carrier and timing recovery are done by digital PLLs, improving detection accuracy.
3. Matched filtering / correlation — maximises SNR at the sampling instant, minimising bit error rate.
4. Adaptive equalisation — LMS/RLS filters cancel ISI caused by multipath fading.
5. Noise and echo cancellation — adaptive cancellers remove echo, hum and background noise in speech and data links.
6. Diversity combining — signals from several antennas are combined optimally to combat fading.
7. Error detection and correction — Viterbi/turbo decoders correct residual errors, giving near-error-free reception.

Conclusion

DSP replaces drift-prone analog circuitry with stable, programmable algorithms. It gives higher SNR, lower bit error rate, greater bandwidth efficiency, flexibility through software upgrade, and repeatable, distortion-free performance — which is why it is the backbone of modern communication systems such as 4G/5G, satellite links and digital broadcasting.

(a) What is knowledge representation? [1 mark]

Knowledge representation is the branch of artificial intelligence concerned with how facts, beliefs, rules and relationships about the real world are stored in a form that a computer can use to reason with. It encodes real-world knowledge into symbols and structures so that an intelligent system can draw inferences and solve problems.

(b) Different knowledge representation techniques [4 marks]

1. Logical representation — Knowledge is written as formal logic (propositional or predicate logic). Facts are assertions and new facts are derived by inference rules such as modus ponens and resolution. It is precise and unambiguous, but can become unwieldy for large domains.

2. Semantic network — Knowledge is represented as a graph of nodes (objects, concepts, events) connected by labelled arcs (relations such as is-a, has-part, owns). It is easy to visualise and supports inheritance, but lacks formal semantics and becomes inefficient as the network grows.

3. Frame representation — Knowledge is organised into frames: record-like structures with slots and slot values describing an object or situation. Frames support default values and inheritance through an is-a hierarchy, making them suitable for structured, stereotyped knowledge.

4. Production rules — Knowledge is expressed as condition–action rules of the form IF condition THEN action. A rule base plus an inference engine performs forward or backward chaining. This is widely used in expert systems because rules are modular and easy to update.

5. Scripts and conceptual dependency — Scripts describe stereotyped sequences of events (for example, visiting a restaurant) with roles, props and scenes. They help a system understand narrative text by filling in expected events.

6. Ontologies and description logics — A formal, shared specification of concepts, properties and individuals in a domain (for example, OWL ontologies). They give machine-readable, reusable and reasoning-capable knowledge, and are the basis of the Semantic Web.

(c) Discussion [5 marks]

Each technique trades off expressiveness, reasoning power and computational cost. Logical representation is the most expressive and has a sound formal basis, so it is used where correctness matters, but full first-order reasoning is undecidable and slow. Semantic networks and frames are easy to build and read and naturally capture hierarchy and defaults, but their meaning is informal, so they can give inconsistent or non-monotonic results. Production rules are simple, modular and explainable — the user can be shown which rule fired — which is why they dominate rule-based expert systems such as MYCIN; their weakness is that a large rule base suffers from conflicting rules and inefficient matching. Scripts are strong for narrative understanding but are domain-specific and brittle when events deviate from the expected pattern. Ontologies provide shared vocabulary and automated classification, but building and maintaining them requires considerable effort and careful design.

In practice, real systems combine techniques: an ontology defines the domain vocabulary, frames or semantic networks hold the objects, and production rules or logic supply the inference. The choice depends on the nature of the domain, the kind of reasoning required, the size of the knowledge base and the acceptable response time.

1. Direct Memory Access (DMA) — Definition (1 mark)

Direct Memory Access (DMA) is a data-transfer technique in which a specialised hardware unit called the DMA controller transfers data directly between an I/O device (or peripheral) and main memory without the continuous involvement of the CPU. The CPU only initialises the transfer (giving the starting address, word count and direction) and is informed by an interrupt when the whole block has been transferred. Thus the CPU is bypassed as the data carrier, and the DMA controller itself becomes the bus master during the transfer.

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2. Internal Components and Registers of a Standard DMA Controller (3 marks)

A standard DMA controller (e.g. the Intel 8237) contains the following units:

Registers

Internal Components

• Data Bus Buffer / Data Register — temporarily holds the data word being moved between memory and the peripheral, and interfaces the controller to the system data bus.
• Address Bus Buffer / Address Latch — drives the memory address onto the address bus during a DMA cycle.
• Control Logic / Timing & Control Unit — generates the bus request (HOLD/BR) and bus grant (HLDA/BG) signals, read/write control signals, and sequences the DMA cycle.
• Priority Encoder / Arbitration Logic — resolves simultaneous requests from several channels and selects the highest-priority channel.
• Channel Logic (multiple channels) — each channel has its own address register and word-count register, allowing several devices to be served.
• Interrupt Logic — sends an interrupt to the CPU when the word count reaches zero or an error occurs.

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3. Burst Mode vs Cycle Stealing Mode (3 marks)

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4. Evaluation: DMA vs Interrupt-Driven I/O (3 marks)

Interrupt-driven I/O: the CPU reads/writes one word per interrupt. For every word the device must raise an interrupt, the CPU must save its context, execute the ISR, transfer the word through a CPU register, restore the context and resume. The data path is device → CPU register → memory, so the CPU executes several instructions per word.

DMA: the CPU executes only two instructions per block — one to set up the DMA controller and one to handle the completion interrupt. The data path is device → memory directly, with the DMA controller acting as bus master.

Comparison:

Conclusion: DMA is far more efficient for bulk, high-speed transfers because it eliminates the per-word interrupt overhead and the double data movement through the CPU. The CPU's utilisation rises sharply, and system throughput improves. Its limitations are the extra hardware cost of the controller, the bus-arbitration (cycle-stealing) delay imposed on the CPU, and the need for cache-coherence handling in systems with cache memory. For small, infrequent transfers, interrupt-driven I/O remains simpler and adequate.

Systolic Arrays and High-Performance Parallel Processing

1. Contribution of Systolic Arrays to High-Performance Parallel Processing

A systolic array is a regular, homogeneous network of simple processing elements (PEs) in which data is rhythmically pumped from PE to PE in step with a global clock — much like blood pumped by the heart through the circulatory system. Each PE performs a simple operation (usually multiply–accumulate) and passes partial results to its neighbours. This regular data flow gives systolic arrays their distinctive contribution to high-performance parallel processing:

• Massive parallelism with simple cells. Hundreds or thousands of identical PEs work simultaneously on different parts of the same computation. Since each PE is small (a multiplier, an adder, a register), the array achieves very high throughput without complex control logic.
• Regular and local communication. Data moves only between adjacent PEs; there are no long, irregular interconnections. This keeps wiring short, reduces capacitance and delay, and allows very high clock rates.
• Pipelined data flow. Inputs are fed in a skewed or staggered manner so that each PE receives a new operand every cycle. Operations overlap in time, so the array produces one result per cycle after the pipeline fills — a classic example being matrix multiplication, where an n × n array computes C = A × B in O(n) time instead of O(n³).
• High computation-to-I/O ratio. Data is reused many times as it flows through the array (each element of A and B is used n times), so memory bandwidth is not the bottleneck — the classic limitation of von Neumann machines.
• Regularity and scalability. The same cell design is replicated; larger problems use larger arrays or multiple passes, making VLSI implementation cheap and predictable.
• Fault tolerance potential. Because cells are identical and locally connected, defective PEs can be bypassed and spare PEs switched in.

Typical applications include matrix multiplication, convolution, FIR/IIR filtering, FFT, image and signal processing, and — most famously today — Google's Tensor Processing Unit (TPU), whose 256 × 256 systolic array of multiply–accumulate cells accelerates deep-learning matrix operations.

2. Architectural Advantages

3. Limitations and Architectural Challenges

• Problem-specific design. A systolic array is efficient only for regular, data-flow computations (matrix/vector operations, convolution). Irregular or data-dependent algorithms map poorly.
• I/O bandwidth bottleneck. Although internal reuse is high, feeding and draining the array at full speed requires very high external bandwidth; the array often stalls waiting for data.
• Clock skew and synchronization. A single global clock over a large array causes skew; the slowest PE limits the clock rate.
• Low utilization for small problems. Pipeline fill/drain overhead means efficiency drops when the problem size is smaller than the array.
• Rigid data flow. Fixed interconnection patterns make the array inflexible for general-purpose computing; control and branching are difficult.
• Fault handling complexity. Although bypass is possible, reconfiguration logic adds overhead and reduces the regularity advantage.
• Programming difficulty. Mapping algorithms onto systolic arrays requires careful transformation (loop skewing, retiming), which is not automatic.

4. Analysis in the Context of Modern Parallel Processing

In modern parallel processing, systolic arrays occupy a specialized accelerator niche rather than replacing general-purpose CPUs or GPUs:

• Strengths today: With the rise of deep learning, the regular, dense matrix operations of neural networks map perfectly onto systolic arrays. TPUs and similar AI accelerators demonstrate that systolic arrays deliver very high TOPS/watt for matrix multiplication — far better than general-purpose cores for this workload.
• Weaknesses today: Modern workloads are increasingly irregular (sparse matrices, graph processing, dynamic control flow). GPUs, with their flexible SIMT model and large memory hierarchy, handle such workloads better. Systolic arrays struggle here because their data flow is fixed at design time.
• Architectural trade-off: Systolic arrays trade flexibility for efficiency. They win when the computation is regular and data reuse is high; they lose when the computation is irregular or memory-bound.
• Hybrid trend: Modern designs combine systolic arrays as coprocessors (e.g., TPU alongside a host CPU) or use reconfigurable systolic fabrics (FPGA-based) to regain some flexibility. Research into sparse systolic arrays and dataflow architectures aims to extend their applicability.

Conclusion: Systolic arrays contribute to high-performance parallel processing through regular, locally connected, pipelined arrays of simple PEs that exploit massive parallelism and data reuse. Their architectural advantages — simplicity, scalability, and high throughput — make them ideal for regular, compute-intensive tasks such as matrix multiplication and neural-network acceleration. However, their rigidity, I/O bottleneck, and poor fit for irregular workloads limit them to specialized roles. In modern parallel processing, they are best viewed as high-efficiency accelerators used alongside general-purpose processors, not as a universal replacement.

१. Role of PLDs in embedded systems and modern digital design

A Programmable Logic Device (PLD) is an IC whose internal logic is not fixed by the manufacturer but is configured by the user after fabrication. It contains arrays of AND/OR gates, flip-flops and programmable interconnects.

Main types: PROM, PLA (programmable AND and OR arrays), PAL (programmable AND, fixed OR), GAL (re-programmable, electrically erasable PAL), CPLD (several PAL-like blocks joined by a switch matrix) and FPGA (array of look-up tables, flip-flops, block RAM, DSP blocks and routing).

Role in embedded systems

• Glue logic: one CPLD replaces many discrete TTL/CMOS chips (address decoding, bus interfacing, level control), cutting board area and cost.
• Hardware acceleration: FPGAs run signal/image processing, encryption and motor control in parallel, faster than a sequential microcontroller.
• Custom peripherals / SoC: soft-core processors (e.g. MicroBlaze, Nios II) and custom UART, SPI or PWM blocks can be built on one chip.
• Reconfigurability: the design can be updated in the field by loading a new bitstream, which helps in long-life products such as telecom and industrial controllers.
• Deterministic timing and fast response compared with software on a CPU.

Role in modern digital system design

• Rapid prototyping and short time-to-market, since no mask or fabrication cost is involved (unlike an ASIC).
• Design with HDLs (VHDL/Verilog), simulation and synthesis, so bugs are fixed by re-programming.
• Low non-recurring cost for low and medium volumes; used to verify an ASIC design before fabrication.
• Used in networking, communications, defence, medical and automotive electronics.

Limitations: higher unit cost, power consumption and lower speed than a full-custom ASIC at high volume.

२. Distance Vector Routing Algorithm

In distance vector routing (basis of RIP, using the Bellman-Ford equation) every router keeps a table (vector) of the distance to every destination and the next hop. Each router:

1. starts knowing only the cost to its directly connected neighbours (others are $\infty$);
2. periodically sends its whole vector only to its neighbours;
3. on receiving a neighbour's vector, updates each entry using

$D_x(y)=\min_{v}\{\,c(x,v)+D_v(y)\,\}$

where $c(x,v)$ is the link cost to neighbour $v$ and $D_v(y)$ is $v$'s advertised distance to $y$; 4. repeats until no table changes (convergence).

Example. Network of routers A to E with link costs A-B = 2, A-C = 5, B-C = 2, B-D = 3, C-D = 2, C-E = 4, D-E = 1.

Initial vector of A: B = 2, C = 5, D = $\infty$, E = $\infty$.

After neighbours' vectors are received, A recalculates:

• to C: $\min(5,\ 2+2)=4$ (via B)
• to D: $\min(2+3,\ 5+2)=5$ (via B)
• to E: $\min(2+\infty,\ 5+4)=9$ in the first exchange; after B learns B-D-E = 4 and re-advertises, A gets $2+4=6$ (via B).

Converged distance table (cost, next hop):

Features and drawbacks: simple and needs only neighbour information, but converges slowly and suffers from the count-to-infinity problem after a link failure. Remedies are split horizon, poison reverse, hold-down timers and a small maximum hop count (RIP uses 15).

1. Fundamental Characteristics of a Distributed System vs. Centralized Architecture

A centralized system keeps all processing, storage and control at one node (mainframe or single server); users connect to that one point. A distributed system is a collection of independent computers that appear to users as a single coherent system. The distinguishing characteristics are:

In short: a distributed system trades the simplicity, easy consistency and easy security of centralization for scalability, availability, fault tolerance and transparency.

2. IaaS vs. PaaS vs. SaaS

Definitions

• IaaS (Infrastructure as a Service): The provider supplies raw computing infrastructure — virtual machines, storage, networks, load balancers — on a pay-as-you-go basis. The customer manages the OS, middleware, runtime and applications. Example: AWS EC2, Microsoft Azure VMs, Google Compute Engine.
• PaaS (Platform as a Service): The provider supplies a ready platform — OS, runtime, database, web server, development and deployment tools — on which the customer deploys its own application code. Example: Google App Engine, Heroku, AWS Elastic Beanstalk.
• SaaS (Software as a Service): The provider delivers a complete, ready-to-use application over the internet; the customer only uses it and manages data/users. Example: Gmail, Google Workspace, Salesforce, Zoom.

Contrast

The three form a stack: IaaS gives the foundation, PaaS adds the development environment on top of it, and SaaS adds the application on top of that. As you move from IaaS to SaaS, management burden and control both decrease.

3. Public, Private and Hybrid Cloud Deployment Models

• Public cloud: Infrastructure is owned and operated by a third-party provider and shared among many tenants over the internet (AWS, Azure, Google Cloud). Merits: no capital cost, elastic scale, pay-per-use. Demerits: less control, multi-tenancy and data-residency concerns.
• Private cloud: Infrastructure is dedicated to a single organization, hosted on-premises or by a provider, with a private network (VMware vSphere, OpenStack). Merits: maximum control, security, compliance and customization. Demerits: high capital and maintenance cost, limited elasticity.
• Hybrid cloud: A combination of public and private clouds joined by secure connectivity, with workloads placed where they fit best (e.g., sensitive data private, web front-end public). Merits: balance of cost, scalability and control; supports cloud bursting and disaster recovery. Demerits: integration, networking and management complexity.

Comparison

In practice, most large organizations — including banks and government bodies — adopt a hybrid model: regulated core systems stay in a private cloud while public cloud is used for scalable, non-sensitive services.

Common Gateway Interface (CGI) and Its Role in Dynamic Web Pages

Common Gateway Interface (CGI) is a standard protocol that defines how a web server communicates with an external program (called a CGI script or gateway program) to generate web content dynamically. When a browser requests a resource that requires server-side processing, the web server executes the CGI program, passes the request data (such as form input) to it through environment variables or standard input, and returns the program's output back to the browser as an HTML response.

Role of CGI in creating dynamic web pages:

1. Bridging the web server and application programs – CGI acts as an interface between the HTTP server (e.g., Apache) and external programs written in languages like Perl, C, or Python. The server itself only serves static files; CGI lets it invoke programs that produce content on the fly.
2. Processing user input – Data submitted through HTML forms (GET or POST) is forwarded to the CGI script, which can validate, store, or manipulate it (e.g., login verification, search queries, feedback forms).
3. Generating customized output – The script builds an HTML page based on the request (user identity, database records, time, etc.), so each user sees different, up-to-date content rather than a fixed page.
4. Database interaction – CGI programs connect to databases to insert, retrieve, or update records, enabling applications such as online registration, e-commerce, and content management.
5. Stateless request handling – Each CGI invocation is independent; the server starts the program, gets the result, and terminates it. This makes CGI simple and portable but also resource-heavy for high-traffic sites.

In short, CGI was the earliest widely used mechanism that turned the web from a static document system into an interactive, application-driven platform.

Use of PHP and Java for Internet Programming

PHP (Hypertext Preprocessor):

• PHP is an open-source, server-side scripting language designed specifically for web development. It is embedded directly within HTML using tags such as <?php ... ?>.
• It runs on the web server (via modules like mod_php or FastCGI) and generates HTML output sent to the client.
• It supports form handling, sessions, cookies, file uploads, and database connectivity (MySQL, PostgreSQL, etc.), making it ideal for dynamic sites, blogs, and e-commerce platforms.
• Being interpreted and easy to learn, PHP offers rapid development and wide hosting support (e.g., WordPress, Facebook's early stack).

Java for Internet Programming:

• Java is an object-oriented, platform-independent language used for both server-side and client-side web programming.
• Server-side: Technologies like Servlets, JSP (Java Server Pages), and frameworks (Spring, Struts) run inside a servlet container (Tomcat, Jetty) to build robust, scalable, secure enterprise web applications. JSP mixes HTML with Java code, similar in spirit to PHP.
• Client-side: Java Applets (now largely obsolete) ran inside browsers; today Java is used for Android apps, web services (REST/SOAP), and backend APIs.
• Java's strengths are strong typing, multithreading, portability (JVM), and a rich library ecosystem, which suit large, high-traffic, transaction-oriented systems.

Comparison in brief: PHP is lightweight, quick to learn, and tightly coupled to web hosting, while Java offers greater structure, scalability, and enterprise-grade security at the cost of more complex setup. Both are widely used to create dynamic, database-driven web applications on the Internet.

Construction of a BJT

A Bipolar Junction Transistor (BJT) is a three-terminal, three-layer semiconductor device formed by sandwiching either two n-type or two p-type layers around one opposite-type layer. It has two basic types:

• NPN transistor — a thin p-type layer (base) sandwiched between two n-type layers (emitter and collector).
• PNP transistor — a thin n-type layer (base) sandwiched between two p-type layers (emitter and collector).

The three regions are:

1. Emitter (E): Heavily doped so it can supply a large number of majority charge carriers. It is moderately sized.
2. Base (B): Very thin and lightly doped so that most carriers injected from the emitter can pass through to the collector without recombining.
3. Collector (C): Moderately doped and physically the largest region, so it can dissipate the heat produced when it collects the carriers.

Because of these two p-n junctions, a BJT has three terminals — emitter, base and collector — giving two junctions: the emitter-base (E-B) junction and the collector-base (C-B) junction.

Operation of a BJT (NPN in active mode)

For normal amplification the transistor is biased in the active region:

• The emitter-base junction is forward biased (for an NPN transistor, battery (V_{BE}) with its positive terminal to the base and negative terminal to the emitter; a PNP transistor needs the opposite polarity).
• The collector-base junction is reverse biased (battery (V_{CB}) with positive terminal to collector, negative to base).

Because the E-B junction is forward biased, the majority carriers of the emitter (electrons in an NPN) are injected into the base. Since the base is very thin and lightly doped, only about 1–5% of these electrons recombine with holes in the base, giving a small base current (I_B). The remaining 95–99% of the electrons diffuse across the base and reach the reverse-biased C-B junction, where the strong junction field sweeps them into the collector, giving the collector current (I_C).

By Kirchhoff's current law,

$I_E = I_C + I_B$

The ratio (\alpha = I_C/I_E) (current gain in common-base) is close to 1, and (\beta = I_C/I_B) (current gain in common-emitter) is typically 20–500. A small change in base current therefore produces a large change in collector current, so the BJT acts as a current amplifier and, with proper load resistance, as a voltage amplifier.

In the cut-off region both junctions are reverse biased and the transistor acts as an open switch; in saturation both junctions are forward biased and it acts as a closed switch. These two regions are used in switching applications.

TU BBS — Officer (Level 7)

1. Object-Oriented Programming Concepts and Modular Program Design in C/C++ (2 marks)

Object-Oriented Programming (OOP) organises a program around objects (data + the functions that operate on it) rather than around procedures. Its four pillars are:

• Encapsulation — bundling data and methods into a class and hiding internal state behind access specifiers (private, protected, public).
• Abstraction — exposing only the essential interface and hiding implementation detail.
• Inheritance — deriving a new class from an existing one, reusing and extending its members.
• Polymorphism — the same interface behaving differently; achieved through function overloading, operator overloading, and virtual functions (runtime/dynamic binding).

Modular program design means decomposing a large program into small, independent, well-defined units. In C this is done with functions grouped into header (.h) and source (.c) files; in C++ additionally with classes, namespaces and templates. Each module exposes only its interface (declarations in the header) while its implementation stays in the source file. Benefits: reusability, easier debugging and testing, parallel development, information hiding, and lower maintenance cost. A module should have high cohesion (one clear job) and low coupling (few dependencies on other modules).

// shape.h  — interface
class Shape {
public:
    virtual double area() const = 0;   // abstraction + polymorphism
    virtual ~Shape() {}
};
// circle.h — a separate module
class Circle : public Shape {          // inheritance
    double r;
public:
    Circle(double r) : r(r) {}
    double area() const override { return 3.14159 * r * r; }
};

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2. Implementation and Applications of Stacks, Queues and Binary Trees (3 marks)

Stack (LIFO — Last In, First Out)

Implemented over an array with a top index, or over a linked list with insertion/deletion at the head. Core operations: push, pop, peek, isEmpty.

#define MAX 100
int stack[MAX], top = -1;
void push(int x) { if (top < MAX-1) stack[++top] = x; }
int  pop(void)   { return (top >= 0) ? stack[top--] : -1; }

Applications: expression conversion (infix → postfix/prefix) and evaluation, function-call management (recursion), undo/redo, backtracking (maze, N-queens), syntax parsing, browser history.

Queue (FIFO — First In, First Out)

Implemented as a circular array (front, rear) or a linked list with front/rear pointers. Operations: enqueue, dequeue, peek. Variants: circular queue (avoids wasted space), priority queue, deque.

int q[MAX], front = -1, rear = -1;
void enqueue(int x){
    if ((rear+1)%MAX == front) return;          // full
    if (front == -1) front = 0;
    rear = (rear+1)%MAX; q[rear] = x;
}
int dequeue(void){
    if (front == -1) return -1;
    int v = q[front];
    if (front == rear) front = rear = -1;
    else front = (front+1)%MAX;
    return v;
}

Applications: CPU/disk/print scheduling, BFS traversal, buffering in I/O and networks, call-centre and ticket queues, rate limiting.

Binary Tree

A hierarchical structure where each node has at most two children (left, right). A Binary Search Tree (BST) keeps left < root < right. Node:

struct Node { int data; struct Node *left, *right; };

Traversals: inorder (sorted order for a BST), preorder, postorder, level-order (uses a queue). Search/insert/delete cost O(log n) when balanced, O(n) when skewed.

Applications: BST and balanced trees (AVL, Red-Black) for indexing and dictionaries, expression trees, Huffman coding, file-system and DOM hierarchies, priority scheduling (heaps), database indexing (B-trees).

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3. Relational Database Design and Normalization up to 3NF (2 marks)

Relational design models data as relations (tables) of tuples with a schema, keys (primary, candidate, foreign), and integrity constraints (entity, referential, domain). A good design removes redundancy and update/insert/delete anomalies.

Normalization is the step-by-step decomposition of relations into well-formed ones:

• 1NF — every attribute holds atomic values; no repeating groups or multi-valued attributes.
• 2NF — in 1NF and no partial dependency: every non-key attribute depends on the whole primary key (relevant when the key is composite).
• 3NF — in 2NF and no transitive dependency: no non-key attribute depends on another non-key attribute. Equivalently, for every FD X → A, either X is a superkey or A is prime.

Example. Enroll(StudentID, CourseID, StudentName, CourseName, Instructor)

• FDs: StudentID → StudentName; CourseID → CourseName, Instructor.
• Violates 2NF (StudentName depends only on part of the key).
• Decompose to 3NF:

Each resulting relation is in 3NF: no partial and no transitive dependencies remain.

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4. Relational Algebra, SQL Query Facilities and Concurrency Control (3 marks)

Relational Algebra

A procedural query language with these core operators on relations:

Example: names of students enrolled in "DBMS":

$\pi_{StudentName}\big(\sigma_{CourseName='DBMS'}(Student \bowtie Enroll \bowtie Course)\big)$

SQL Query Facilities

SQL is a declarative language with these facilities:

• DDL — CREATE, ALTER, DROP for schema definition.
• DML — SELECT, INSERT, UPDATE, DELETE for data manipulation.
• DCL — GRANT, REVOKE for access control.
• TCL — COMMIT, ROLLBACK, SAVEPOINT for transactions.
• Aggregate & grouping — COUNT, SUM, AVG, MIN, MAX, GROUP BY, HAVING.
• Joins & subqueries — inner/outer joins, nested SELECT, EXISTS, IN.
• Views & constraints — CREATE VIEW, PRIMARY KEY, FOREIGN KEY, CHECK.

SELECT s.StudentName, AVG(m.Marks) AS AvgMarks
FROM Student s JOIN Marks m ON s.StudentID = m.StudentID
GROUP BY s.StudentName
HAVING AVG(m.Marks) > 60
ORDER BY AvgMarks DESC;

Concurrency Control Mechanisms

When multiple transactions run concurrently, problems such as lost update, dirty read, and unrepeatable read arise. Mechanisms to preserve ACID properties:

• Locking — shared (read) and exclusive (write) locks; two-phase locking (2PL) guarantees serializability. Strict 2PL avoids cascading rollbacks.
• Timestamp ordering — each transaction gets a timestamp; conflicting operations are ordered by timestamp and offending transactions are aborted.
• Optimistic concurrency control — read, validate, then write; abort on conflict at commit time.
• Multiversion concurrency control (MVCC) — keeps multiple versions so readers never block writers.
• Deadlock handling — prevention (wait–die, wound–wait), detection via wait-for graph, or timeout and rollback.
• Isolation levels — Read Uncommitted, Read Committed, Repeatable Read, Serializable, trading consistency against concurrency.

Process Scheduling in an Operating System

Concept of Process Scheduling

Process scheduling is the activity of the operating system that decides which process in the ready queue will be allocated the CPU next, and for how long. Since a computer normally has fewer CPUs than the number of processes competing for them, the OS must arbitrate this competition in an orderly, fair and efficient manner. The component of the OS that performs this task is called the scheduler (or dispatcher-scheduler), and the algorithm it follows is called the scheduling algorithm or scheduling policy.

The main objectives of process scheduling are:

1. Maximize CPU utilization — keep the CPU as busy as possible.
2. Maximize throughput — complete as many processes per unit time as possible.
3. Minimize turnaround time — reduce the total time from submission to completion of a process.
4. Minimize waiting time — reduce the time a process spends waiting in the ready queue.
5. Minimize response time — give quick first response, important in interactive systems.
6. Ensure fairness — every process should get a fair share of CPU time.
7. Enforce priority and meet deadlines — important in real-time systems.

Scheduling decisions are made at four points: when a process switches from running to waiting (I/O request), from running to ready (interrupt), from waiting to ready (I/O completion), and when a process terminates. If scheduling is done only in the first and fourth cases, it is called non-preemptive (the running process keeps the CPU until it blocks or finishes). If scheduling is also done in the second and third cases, it is called preemptive (the running process can be forcibly removed).

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Types of Scheduling Algorithms

1. First Come First Served (FCFS)

Features: The ready queue is a simple FIFO queue. The process that arrives first is served first. It is non-preemptive.

Merits: Simple to understand and implement; no starvation; low overhead.

Demerits: Suffers from the convoy effect — a long CPU-bound process at the head blocks all short processes behind it, raising average waiting time. Poor for time-sharing systems.

Suitability: Batch systems where response time is not critical and jobs are roughly of similar length.

2. Shortest Job First (SJF)

Features: The process with the smallest next CPU burst is selected. It may be non-preemptive (Shortest Job First) or preemptive (Shortest Remaining Time First, SRTF). It is provably optimal in terms of minimum average waiting time.

Merits: Gives the minimum average waiting time; good throughput for batch jobs.

Demerits: The length of the next CPU burst is difficult to know in advance (must be estimated); starvation of long processes is possible; preemptive version needs frequent comparisons.

Suitability: Batch environments where burst times can be estimated statistically (e.g., using exponential averaging).

3. Priority Scheduling

Features: Each process is assigned a priority; the CPU goes to the highest-priority ready process. It can be preemptive or non-preemptive. Priorities may be static or dynamic.

Merits: Allows important/system processes to be served first; flexible — priority can reflect urgency, user class, or resource needs.

Demerits: Starvation of low-priority processes; indefinite blocking. Solved by aging (gradually increasing the priority of waiting processes).

Suitability: Systems with clearly differentiated classes of work — real-time systems, OS kernel tasks, and time-sharing systems with user priority.

4. Round Robin (RR)

Features: Designed for time-sharing. Each process gets the CPU for a fixed time quantum (typically 10–100 ms); if it does not finish, it is preempted and placed at the tail of the ready queue. It is preemptive.

Merits: Fair — every process gets periodic CPU time; good response time; no starvation.

Demerits: Performance depends heavily on quantum size. If quantum is too small, too many context switches (overhead); if too large, it degenerates into FCFS. Average waiting time is often higher than SJF.

Suitability: Interactive time-sharing and general-purpose multi-user systems.

5. Multilevel Queue Scheduling

Features: The ready queue is partitioned into several separate queues (e.g., system processes, interactive, batch). Each queue has its own scheduling algorithm and priority. Scheduling between queues may be fixed-priority or time-sliced.

Merits: Good separation of process classes; system and interactive processes get fast service.

Demerits: Starvation of lower-priority queues under fixed priority; inflexible — a process cannot move between queues.

Suitability: Systems with distinct, well-defined categories of processes.

6. Multilevel Feedback Queue

Features: Like multilevel queue but processes can move between queues based on behaviour and aging. Typically, a new process enters the highest-priority queue; if it uses too much CPU, it is demoted; if it waits too long, it is promoted. Parameters: number of queues, algorithm per queue, promotion/demotion rules, entry queue.

Merits: Most flexible; adapts to process behaviour; prevents starvation through aging; favours short and interactive jobs.

Demerits: Complex to implement and tune; many parameters must be chosen correctly.

Suitability: General-purpose modern OS (e.g., Unix, Windows) where a mix of interactive and batch processes must be handled.

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Comparative Summary

In practice, real operating systems use multilevel feedback queue variants because they combine the merits of several algorithms — quick response for interactive jobs, fairness for all, and protection against starvation — while accepting greater implementation complexity.