Electronics and Electrical Safety

Electric shock is the physiological reaction of the body when electric current passes through it, caused by contact between a part of the body and a live conductor while another part is at earth (or at a different potential). The severity depends on the current magnitude, its path through the body, duration, frequency and the body resistance at the contact points.

Effects as the current (50 Hz AC, hand-to-foot) increases:

Order of effects: perception, then mild shock, then painful shock with loss of muscular control (cannot let go), then respiratory difficulty/paralysis, then ventricular fibrillation, then cardiac arrest and severe burns. Ventricular fibrillation is the most dangerous because it can occur at currents well below those that cause burns.

Successive Approximation ADC

The successive approximation ADC is the most widely used method for medium-to-high speed, medium-resolution conversion. It works on the principle of binary search — instead of counting up from zero (as in a counter-type ADC), it compares the input against a trial voltage and narrows down the digital value bit by bit, starting from the MSB.

Main blocks:

1. Sample-and-Hold (S/H) circuit — samples the analog input and holds it constant during conversion.
2. Comparator — compares the held input voltage $V_{in}$ with the DAC output $V_{DAC}$.
3. Successive Approximation Register (SAR) — an N-bit register that supplies the trial digital word and is controlled by the comparator output.
4. N-bit DAC — converts the SAR contents back to analog for comparison.
5. Control logic / clock — sequences the register and generates the end-of-conversion (EOC) signal.

Working principle (for an N-bit ADC):

1. The S/H circuit holds the analog input $V_{in}$.
2. The SAR is reset to all zeros. The MSB is set to 1, giving the trial word $100\ldots0$, whose DAC output is $V_{FS}/2$.
3. The comparator checks whether $V_{in} \geq V_{DAC}$:
   • If yes, the MSB is retained (kept at 1).
   • If no, the MSB is cleared back to 0.
4. The next lower bit is set to 1 and the comparison repeated. The DAC output now equals the sum of the retained bits plus the newly tried bit.
5. This continues down to the LSB. After N comparisons, the SAR holds the N-bit digital equivalent of $V_{in}$, and the EOC signal indicates that the output is valid.

Example (3-bit ADC, $V_{FS} = 8\ \text{V}$, $V_{in} = 5.2\ \text{V}$):

Final output: 101 (decimal 5), with quantization error $= 5.2 - 5.0 = 0.2\ \text{V}$, which is within $\pm \tfrac{1}{2}\text{LSB} = \pm 0.5\ \text{V}$.

Conversion time: If the clock period is $T_{clk}$, the total conversion time is $T_c = N \cdot T_{clk}$ which is fixed and independent of the input magnitude — a major advantage over counter-type ADCs, whose time varies with $V_{in}$.

Advantages:

• Conversion time is constant and much shorter than ramp/counter type.
• Good accuracy and resolution for moderate cost.
• Simple, compact circuit; easily implemented in IC form.

Limitations:

• Slower than flash ADC.
• Needs a precise DAC and comparator; accuracy depends on DAC linearity.
• Not suitable for very high-speed applications.

Applications: Data acquisition systems, digital multimeters, microcontrollers (built-in ADC), instrumentation and process control.