Digital Logic System

Flip-flop. A flip-flop is a bistable sequential circuit. It has two stable states (0 and 1) and stores one bit of information. Its output depends on the present inputs and the previous state, and it changes state only when a clock pulse arrives. It is the basic memory element of registers and counters. Types are SR, JK, D and T.

JK flip-flop. The JK flip-flop removes the invalid condition of the SR flip-flop. Its inputs are $J$ (set), $K$ (reset) and the clock $CLK$. Its outputs are $Q$ and $\overline{Q}$.

Logic diagram (clocked SR latch built from NAND gates, with feedback from the outputs)

J ──────────[NAND1]──┐
Q' ─────────┘        [NAND3]──┬── Q
CLK ────────┘                 │ (cross-coupled)
CLK ────────┐                 │
Q ──────────[NAND2]──┐       [NAND4]── Q'
K ──────────┘        └───────┘

$NAND_1$ receives $J, CLK, \overline{Q}$ and $NAND_2$ receives $K, CLK, Q$. Their outputs feed the cross-coupled latch $NAND_3$, $NAND_4$.

Characteristic (truth) table

Characteristic equation

$Q_{n+1} = J\overline{Q_n} + \overline{K}Q_n$

Operation

• $J=K=0$: both NAND gates output 1, so the latch holds its state.
• $J=0,K=1$: only $NAND_2$ is active when $Q=1$, so the flip-flop resets to $Q=0$.
• $J=1,K=0$: only $NAND_1$ is active when $Q=0$, so it sets to $Q=1$.
• $J=K=1$: the output toggles on each clock pulse. This is the feature that SR lacks.

Race-around condition. When $J=K=1$ and the clock pulse is wider than the propagation delay, the output toggles repeatedly during one pulse. This is avoided by using a master-slave or edge-triggered JK flip-flop. Applications include counters, frequency dividers and shift registers.

Don't care condition. For some input combinations of a logic function, the output is not specified because those combinations never occur, or because the output has no effect on the system. Such conditions are called don't care conditions and are marked X (or d) in the truth table or K-map.

Use in simplification. Each X may be treated as 0 or 1, whichever helps to form larger groups in the K-map. This gives a simpler expression with fewer literals and gates. An X is included in a group only if it helps; it is never necessary to cover it.

Example. For $F = \Sigma(1,3,5) + d(7)$ with inputs $A,B,C$, taking $d(7)$ as 1 allows the group $A,B,C$ column with $C=1$:

$F = C$

Without the don't care, the best result would be $\overline{A}C + \overline{B}C$.

Common applications. The unused codes in BCD (1010 to 1111), code converters such as BCD to excess-3, and seven-segment decoders.

Step 1: K-map (rows $AB$, columns $CD$; X = don't care)

Step 2: Grouping

• Quad of m0, m1, m3, m2, m8, m9, m11, m10 (all cells with $B=0$), using the don't cares m2, m3, m9. This gives $\overline{B}$.
• Quad of m0, m4, m12, m8 (column $CD=00$). This gives $\overline{C}\,\overline{D}$.

All the 1s (0, 1, 4, 8, 10, 11, 12) are covered. The don't cares m6, m15 are left as 0.

$F = \overline{B} + \overline{C}\,\overline{D}$

Step 3: NOR-only implementation

Using $\overline{C}\,\overline{D} = \overline{C + D}$:

$F = \overline{B} + \overline{C+D}$

An OR is a NOR followed by a NOR used as an inverter, so four 2-input NOR gates are enough:

1. $G_1 = \text{NOR}(B,B) = \overline{B}$
2. $G_2 = \text{NOR}(C,D) = \overline{C+D}$
3. $G_3 = \text{NOR}(G_1,G_2) = \overline{\overline{B}+\overline{C+D}}$
4. $G_4 = \text{NOR}(G_3,G_3) = \overline{B} + \overline{C+D} = F$

B ──[NOR]──┐
           [NOR]──[NOR as NOT]── F
C ──[NOR]──┘
D ──┘

Status register (flag register or condition code register). It is a register of the processor whose individual bits, called flags, record conditions produced by the most recent arithmetic or logic operation in the ALU. These flags are used by conditional branch instructions to decide the program flow.

Common flags (4-bit status register)

Working. After an ALU operation, the output carry, the sign bit, an 8-input NOR of the result bits (for zero) and the exclusive-OR of the last two carries (for overflow) are loaded into the flip-flops of the status register.

Uses. Conditional jumps (branch if zero, branch if carry), comparison of numbers, and checking for overflow in signed arithmetic. Larger processors add more flags such as parity, auxiliary carry, interrupt enable and trap.

Half adder. It adds two bits $x$ and $y$:

$S = x\oplus y,\qquad C = xy$

It is one XOR gate and one AND gate.

Full adder from two half adders and an OR gate

A full adder adds $A$, $B$ and $C_{in}$:

$S = A\oplus B\oplus C_{in},\qquad C_{out} = AB + C_{in}(A\oplus B)$

1. Half adder 1 adds $A$ and $B$: $S_1 = A\oplus B$, $C_1 = AB$.
2. Half adder 2 adds $S_1$ and $C_{in}$: $S = S_1\oplus C_{in}$, $C_2 = S_1C_{in}$.
3. OR gate combines the two carries: $C_{out} = C_1 + C_2 = AB + C_{in}(A\oplus B)$.

A ──┐                  S1 ──┐
    [HA 1]── S1 ────────── [HA 2]── S (Sum)
B ──┘   └─ C1 ──┐   Cin ──┘   └─ C2 ──┐
                [   OR   ]────────────  Cout

Verification. For $A=1,B=1,C_{in}=1$: $S_1 = 0$, $C_1 = 1$; $S = 0\oplus1 = 1$, $C_2 = 0$; $C_{out} = 1+0 = 1$. So $1+1+1 = 11_2$, which is correct. For $A=1,B=0,C_{in}=1$: $S_1=1$, $C_1=0$, $S = 1\oplus1=0$, $C_2=1$, $C_{out}=1$, giving $10_2$, which is correct.

The carry equation matches the sum-of-products form $AB+BC_{in}+AC_{in}$, since $C_{in}(A\oplus B)+AB = AC_{in}+BC_{in}+AB$.

ALU (Arithmetic Logic Unit). The ALU is the part of the CPU that performs all arithmetic and logic operations. It is a combinational circuit with two data inputs ($A$, $B$), function-select lines, a data output $F$, and status outputs (flags).

 A ──┐                ┌──> F (result)
     [   ALU   ]──────┤
 B ──┘  ^            └──> Status flags (C, S, Z, V)
        |
 Function select (opcode)

Operations

1. Arithmetic operations: addition ($A+B$), subtraction ($A-B$ using 2's complement), increment ($A+1$), decrement ($A-1$), negation, and (in larger ALUs) multiplication and division.
2. Logic operations: AND, OR, NOT (complement), XOR and NAND/NOR, done bit by bit on corresponding bits of $A$ and $B$.
3. Shift and rotate operations: logical shift left or right, arithmetic shift, rotate.
4. Comparison: compare two numbers by subtracting them and checking the flags (zero, sign, carry), without storing the result.

Typical function table (select lines $S_1S_0$, mode $M$)

Structure. The arithmetic section uses full adders in a chain, with a MUX to pick $B$, $\overline{B}$, 0 or all 1s. The logic section uses an AND, OR, XOR and NOT gate on each bit with a MUX to pick one output. A final MUX controlled by the mode selects the arithmetic or logic result.

Status flags. Carry (C), Sign (S), Zero (Z) and Overflow (V) are set according to the result and stored in the status register.

SR flip-flop. The SR (Set-Reset) flip-flop is the basic clocked flip-flop with two inputs, $S$ (set) and $R$ (reset), a clock input, and outputs $Q$ and $\overline{Q}$. It stores one bit.

Logic circuit (clocked, NAND based)

S ──┐
    [NAND1]──────┐
CLK ┤            [NAND3]──┬── Q
    [NAND2]──┐   │  ^     │
R ──┘        └── [NAND4]──┴── Q'

$NAND_1$ and $NAND_2$ gate $S$ and $R$ with the clock. Their outputs drive the cross-coupled NAND latch ($NAND_3$, $NAND_4$). When $CLK=0$ the latch holds its value; when $CLK=1$ the inputs $S,R$ act.

Truth (characteristic) table

Operation

• $S=0,R=0$: both clocked gates output 1, so the latch keeps its previous state.
• $S=0,R=1$: the latch is reset, so $Q=0$ and $\overline{Q}=1$.
• $S=1,R=0$: the latch is set, so $Q=1$ and $\overline{Q}=0$.
• $S=1,R=1$: both outputs would be forced to the same value, and the final state after the clock returns to 0 is unpredictable. This combination must be avoided.

Characteristic equation

$Q_{n+1} = S + \overline{R}Q_n,\quad\text{with the constraint } SR = 0$

Limitation. The invalid condition $S=R=1$ is removed in the JK flip-flop.

4-bit ALU design. A 4-bit ALU performs arithmetic and logic operations on two 4-bit operands $A_3A_2A_1A_0$ and $B_3B_2B_1B_0$ and produces a 4-bit result $F_3F_2F_1F_0$. It is built from four identical one-bit stages, each with an arithmetic section and a logic section, plus a mode select.

Arithmetic section. A full adder in each stage adds $A_i$ to $Y_i$ and the carry. A 4:1 MUX chooses $Y_i$ from $B_i$, $\overline{B_i}$, 0 or 1 using select lines $S_1S_0$. The first stage receives carry-in $C_{in}$; the carries ripple to $C_{out}$ of stage 3. The result is $D = A + Y + C_{in}$.

Logic section. Each stage has AND, OR, XOR and NOT gates on $A_i$ and $B_i$, feeding a 4:1 MUX selected by $S_1S_0$.

Complete stage. A mode line $M$ controls a 2:1 MUX at the output: $F_i = D_i$ when $M=0$ (arithmetic) and $F_i = E_i$ when $M=1$ (logic). So 3 control bits $M, S_1, S_0$ (plus $C_{in}$ for arithmetic) select among 8 logic/arithmetic basic functions, or 16 functions with $C_{in}$.

        S1 S0
         |
 A_i --> [Arithmetic: FA + Y-MUX] --D_i--\
 B_i -->                                   [2:1 MUX, M] --> F_i
 A_i --> [Logic: gates + MUX] ---E_i-----/

Operation example. With $M=0$, $S_1S_0=01$, $C_{in}=1$: $F = A + \overline{B} + 1 = A - B$ (2's complement subtraction). With $M=1$, $S_1S_0=00$: $F = A\cdot B$ bit by bit. The carry-out and the result are used to set the status flags.

(a) Using NAND gates only

Apply double complement and De Morgan's law:

$A + BC = \overline{\overline{A + BC}} = \overline{\overline{A}\cdot\overline{BC}}$

So the circuit needs three 2-input NAND gates:

1. $G_1$: NAND with both inputs tied to $A$, giving $\overline{A}$.
2. $G_2$: NAND of $B$ and $C$, giving $\overline{BC}$.
3. $G_3$: NAND of the outputs of $G_1$ and $G_2$, giving $\overline{\overline{A}\cdot\overline{BC}} = A + BC$.

A ──┬──[NAND]── A' ──┐
    └──┘             [NAND]── F = A + BC
B ──[NAND]── (BC)' ──┘
C ──┘

(b) Using NOR gates only

Use the distributive law $A + BC = (A+B)(A+C)$ and De Morgan's law:

$(A+B)(A+C) = \overline{\overline{(A+B)} + \overline{(A+C)}}$

This needs three 2-input NOR gates:

1. $G_1$: NOR of $A$ and $B$, giving $\overline{A+B}$.
2. $G_2$: NOR of $A$ and $C$, giving $\overline{A+C}$.
3. $G_3$: NOR of the outputs of $G_1$ and $G_2$, giving $\overline{\overline{A+B}+\overline{A+C}} = (A+B)(A+C) = A + BC$.

A ──[NOR]── (A+B)' ──┐
B ──┘                 [NOR]── F = A + BC
A ──[NOR]── (A+C)' ──┘
C ──┘

Verification. For $A=0,B=1,C=1$: $F = 0 + 1 = 1$. In the NOR circuit, $G_1=\overline{0+1}=0$ and $G_2=\overline{0+1}=0$, so $F=\overline{0+0}=1$. For $A=0,B=1,C=0$: $G_1=0$, $G_2=\overline{0+0}=1$, so $F=\overline{0+1}=0$, which agrees with $A+BC=0$.

Combinational circuit. A combinational circuit is a logic circuit whose output depends only on the present values of its inputs, not on past inputs. It has no memory or feedback. It is built from gates, and examples are adders, multiplexers, decoders and code converters.

Design of the 2421 to 8 4 -2 -1 converter

Let the inputs be $A B C D$ (2421 code) and the outputs $W X Y Z$ (8 4 -2 -1 code). Input combinations 0101 to 1010 (m5 to m10) never occur in 2421, so they are don't cares.

K-map simplification (don't cares m5 to m10)

• $W$ is 1 for m11 to m15, and the don't cares m8, m9, m10 let one group of the whole $A=1$ half cover them: $W = A$.
• $Z$ is 1 for m1, m3, m11, m13, m15, so $Z = D$.
• $Y$ follows $C \oplus D$ when $A=0$ and the complement when $A=1$, so $Y = A \oplus C \oplus D$.
• $X$ is 1 for m1, m2, m3, m4, m15. Using the don't cares, the groups are $\overline{A}D$ (m1, m3, plus don't cares), $\overline{A}C$ (m2, m3), $\overline{A}B$ (m4) and the pair $BCD$ (m7 with m15).

$W = A,\qquad X = \overline{A}B + \overline{A}C + \overline{A}D + BCD,\qquad Y = A \oplus C \oplus D,\qquad Z = D$

Check. For digit 6, $ABCD=1100$: $W=1$; $X = 0+0+0+0 = 0$; $Y = 1\oplus0\oplus0 = 1$; $Z=0$. This gives 1010, which is 6 in 8 4 -2 -1 code ($8-2=6$). For digit 9, $ABCD=1111$: $X = BCD = 1$, $Y = 1\oplus1\oplus1 = 1$, giving 1111, which is $8+4-2-1=9$.

Implementation. Inputs $A$ and $D$ pass straight through to $W$ and $Z$. Two XOR gates give $Y$. Three AND gates, one 3-input AND and one OR give $X$.

Counter. A counter is a sequential circuit made of flip-flops that goes through a prescribed sequence of states when clock pulses are applied. It is used to count pulses, divide frequency and generate timing. A $n$-bit binary counter has $2^n$ states.

Design of a 3-bit synchronous up counter using D flip-flops (sequence 0 to 7, then back to 0)

For a D flip-flop, the next state equals the input: $D = Q^+$.

K-map simplification

• $D_0 = 1$ for states 000, 010, 100, 110 (those with $Q_0=0$), so $D_0 = \overline{Q_0}$.
• $D_1 = 1$ for states 001, 010, 101, 110 ($Q_1 \ne Q_0$), so $D_1 = Q_1 \oplus Q_0$.
• $D_2 = 1$ for states 011, 100, 101, 110, which gives $D_2 = Q_2\overline{Q_1} + Q_2\overline{Q_0} + \overline{Q_2}Q_1Q_0 = Q_2 \oplus (Q_1Q_0)$.

$D_0 = \overline{Q_0},\qquad D_1 = Q_0 \oplus Q_1,\qquad D_2 = Q_2 \oplus (Q_1Q_0)$

Circuit. Three D flip-flops share a common clock. $Q_0$ feeds back through a NOT gate to $D_0$. An XOR gate (inputs $Q_0, Q_1$) feeds $D_1$. An AND gate ($Q_1Q_0$) and an XOR gate (with $Q_2$) feed $D_2$. The outputs $Q_2Q_1Q_0$ count 000, 001, ..., 111, 000, ... on successive clock pulses.

The XOR function is $Y = A\oplus B = A\overline{B} + \overline{A}B$.

(a) Using NAND gates only (4 gates)

$A\oplus B = \overline{\overline{A\cdot\overline{AB}}\cdot\overline{B\cdot\overline{AB}}}$

1. $G_1 = \overline{AB}$
2. $G_2 = \overline{A\cdot G_1} = \overline{A\,\overline{AB}} = \overline{A}+AB = \overline{A}+B$
3. $G_3 = \overline{B\cdot G_1} = \overline{B}+A$
4. $G_4 = \overline{G_2\cdot G_3} = \overline{(\overline{A}+B)(A+\overline{B})} = A\overline{B}+\overline{A}B$

Simplified: $(\overline{A}+B)(A+\overline{B}) = AB + \overline{A}\,\overline{B}$, whose complement is $A\oplus B$.

A ─┬────────────[NAND2]──┐
   └─[NAND1]─┬───────────  [NAND4]── A⊕B
B ─┬─────────┘            │
   └────────────[NAND3]──┘

(b) Using NOR gates only (5 gates)

$A\oplus B = (A+B)\cdot\overline{AB} = \overline{\overline{A+B} + AB}$

1. $G_1 = \overline{A+B}$ (NOR)
2. $G_2 = \overline{A+A} = \overline{A}$, $G_3 = \overline{B+B} = \overline{B}$ (NOR inverters)
3. $G_4 = \overline{G_2+G_3} = AB$ (NOR)
4. $G_5 = \overline{G_1+G_4} = \overline{\overline{A+B}+AB} = (A+B)\overline{AB} = A\oplus B$

Check for $A=1,B=1$: NAND version gives $G_1=0$, $G_2=1$, $G_3=1$, $G_4=\overline{1\cdot1}=0$. NOR version gives $G_1=0$, $G_4=1$, $G_5=\overline{0+1}=0$. Both are correct for XOR. For $A=1,B=0$: NAND gives $G_1=1$, $G_2=\overline{1\cdot1}=0$, $G_3=1$, $G_4=1$.

Combinational circuit. A combinational circuit is a logic circuit whose outputs depend only on the present inputs, with no memory or feedback. Examples are adders, multiplexers, decoders and code converters.

Design of the 8 4 -2 -1 to BCD converter

Inputs $ABCD$ (8 4 -2 -1 code) and outputs $wxyz$ (BCD). The combinations 0001, 0010, 0011, 1100, 1101, 1110 never occur and are don't cares.

K-map simplification

• $w = \Sigma(8,15)$ with don't cares 12, 13, 14: groups m12 to m15 give $AB$; m8 with m12 gives $A\overline{C}\,\overline{D}$. So $w = AB + A\overline{C}\,\overline{D}$.
• $x = \Sigma(4,9,10,11)$: m1, m3, m9, m11 gives $\overline{B}D$; m2, m3, m10, m11 gives $\overline{B}C$; m4 with m12 gives $B\overline{C}\,\overline{D}$. So $x = \overline{B}C + \overline{B}D + B\overline{C}\,\overline{D}$.
• $y = \Sigma(5,6,9,10)$: m1, m5, m9, m13 gives $\overline{C}D$; m2, m6, m10, m14 gives $C\overline{D}$. So $y = C\oplus D$.
• $z = \Sigma(5,7,9,11,15)$ (the 1s of BCD): all have $D=1$, so $z = D$.

$w = AB + A\overline{C}\,\overline{D},\quad x = \overline{B}C + \overline{B}D + B\overline{C}\,\overline{D},\quad y = C\oplus D,\quad z = D$

Check. Digit 9, $ABCD=1111$: $w = AB = 1$; $x = 0+0+0 = 0$; $y = 0$; $z = 1$, giving 1001. Digit 5, $ABCD=1011$: $w=0$; $x = \overline{B}C = 1$; $y = 1\oplus1=0$; $z=1$, giving 0101.

Implementation. $z$ is a direct wire from $D$, $y$ is one XOR gate, and $w$ and $x$ use AND-OR logic.

Counter. A counter is a sequential circuit built from flip-flops that goes through a fixed sequence of states when clock pulses arrive. It counts pulses and is used for timing, frequency division and addressing.

3-bit synchronous up counter using SR flip-flops (count 000 to 111, then back to 000)

SR excitation table

State table

Simplification by K-map

• $S_0 = 1$ when $Q_0 = 0$, so $S_0 = \overline{Q_0}$; $R_0 = 1$ when $Q_0=1$, so $R_0 = Q_0$.
• $S_1 = 1$ at 001 and 101, so $S_1 = \overline{Q_1}Q_0$; $R_1 = 1$ at 011 and 111, so $R_1 = Q_1Q_0$.
• $S_2 = 1$ only at 011, so $S_2 = \overline{Q_2}Q_1Q_0$; $R_2 = 1$ only at 111, so $R_2 = Q_2Q_1Q_0$.

$S_0=\overline{Q_0},\ R_0=Q_0;\quad S_1=\overline{Q_1}Q_0,\ R_1=Q_1Q_0;\quad S_2=\overline{Q_2}Q_1Q_0,\ R_2=Q_2Q_1Q_0$

In no state are $S$ and $R$ both 1, so the forbidden input never occurs.

Circuit. Three SR flip-flops share a clock. $Q_0$ and $\overline{Q_0}$ drive $R_0$ and $S_0$ directly. Two-input AND gates give $S_1$ and $R_1$, and three-input AND gates give $S_2$ and $R_2$. The outputs count 0 to 7 and repeat.

(i) $(56B)_{16} = (?)_{10}$

$5\cdot16^2 + 6\cdot16 + 11 = 1280 + 96 + 11 = 1387$

$(56B)_{16} = (1387)_{10}$

(ii) $(324)_8 = (?)_{10}$

$3\cdot64 + 2\cdot8 + 4 = 192 + 16 + 4 = 212$

$(324)_8 = (212)_{10}$

(iii) $(11010)_{Gray} = (?)_2$

The MSB is copied; each following binary bit is the previous binary bit XOR the next Gray bit.

• $b_1 = 1$
• $b_2 = 1\oplus1 = 0$
• $b_3 = 0\oplus0 = 0$
• $b_4 = 0\oplus1 = 1$
• $b_5 = 1\oplus0 = 1$

$(11010)_{Gray} = (10011)_2$

(iv) $(9480)_{10} = (?)_2$

$9480 = 8192 + 1024 + 256 + 8 = 2^{13} + 2^{10} + 2^{8} + 2^{3}$.

Division method (remainders from the last upward): $9480/2 = 4740$ r 0; $4740/2 = 2370$ r 0; $2370/2 = 1185$ r 0; $1185/2 = 592$ r 1; $592/2 = 296$ r 0; $296/2 = 148$ r 0; $148/2 = 74$ r 0; $74/2 = 37$ r 0; $37/2 = 18$ r 1; $18/2 = 9$ r 0; $9/2 = 4$ r 1; $4/2 = 2$ r 0; $2/2 = 1$ r 0; $1/2 = 0$ r 1.

$(9480)_{10} = (10010100001000)_2$

(v) $(110)_2 = (?)_{16}$

Pad to 4 bits: $0110 = 6$.

$(110)_2 = (6)_{16}$

(i) $(E1B.AC5)_{16} = (?)_8$

Hex to binary: $E=1110$, $1=0001$, $B=1011$ . $A=1010$, $C=1100$, $5=0101$.

$1110\ 0001\ 1011 . 1010\ 1100\ 0101$

Regroup in 3 bits from the point: integer part $111\ 000\ 011\ 011$ gives $7,0,3,3$; fraction part $101\ 011\ 000\ 101$ gives $5,3,0,5$.

$(E1B.AC5)_{16} = (7033.5305)_8$

(ii) $(237)_8 = (?)_2$

Replace each octal digit by 3 bits: $2=010$, $3=011$, $7=111$.

$(237)_8 = (010011111)_2 = (10011111)_2$

(iii) $(100110101)_{Gray} = (?)_2$

Copy the MSB; then $b_i = b_{i-1}\oplus g_i$.

• $b_1 = 1$
• $b_2 = 1\oplus0 = 1$
• $b_3 = 1\oplus0 = 1$
• $b_4 = 1\oplus1 = 0$
• $b_5 = 0\oplus1 = 1$
• $b_6 = 1\oplus0 = 1$
• $b_7 = 1\oplus1 = 0$
• $b_8 = 0\oplus0 = 0$
• $b_9 = 0\oplus1 = 1$

$(100110101)_{Gray} = (111011001)_2$

(iv) $(1110)_2 = (?)_{10}$

$1\cdot8 + 1\cdot4 + 1\cdot2 + 0\cdot1 = 14$

$(1110)_2 = (14)_{10}$

An asynchronous (ripple) counter applies the clock only to the first flip-flop; each later flip-flop is clocked by the output of the previous one. A 3-bit up/down counter counts $0\to7$ in up mode and $7\to0$ in down mode, selected by a control input $M$.

Basic idea. Use three JK flip-flops with $J=K=1$ (so each toggles on a clock edge), triggered on the falling (negative) edge.

• Up counting: each flip-flop is clocked from the $Q$ output of the previous one. $Q_0$ toggling from 1 to 0 gives a clock edge to the next stage.
• Down counting: each flip-flop is clocked from the $\overline{Q}$ output of the previous one.

Mode selection. A control input $M$ is used ($M=1$ up, $M=0$ down), and the clock of each stage is

$CLK_1 = M\,Q_0 + \overline{M}\,\overline{Q_0},\qquad CLK_2 = M\,Q_1 + \overline{M}\,\overline{Q_1}$

$CLK_0$ is the external clock. These are implemented with two AND gates and an OR gate (a 2-to-1 multiplexer) between successive stages.

Count sequence

Circuit

1. Three JK flip-flops $FF_0,FF_1,FF_2$ with $J=K=1$, falling-edge triggered.
2. External clock to $FF_0$.
3. Multiplexer logic as above in front of $CLK_1$ and $CLK_2$.
4. Outputs $Q_2Q_1Q_0$.

Limitation. The propagation delay accumulates through the stages, so the counter is slower than a synchronous counter and can show brief false states.

A 3-bit synchronous up/down counter counts $0\to7$ when the control input $M=1$ (up) and $7\to0$ when $M=0$ (down). The same clock is applied to all three flip-flops.

Using T-type behaviour (JK flip-flops with $J=K=T$): a flip-flop must toggle when

• counting up: all lower bits are 1,
• counting down: all lower bits are 0.

$T_0 = 1$ $T_1 = M\,Q_0 + M'\,Q_0'$ $T_2 = M\,Q_1Q_0 + M'\,Q_1'Q_0'$

Design (JK flip-flops)

$J_0 = K_0 = 1$ $J_1 = K_1 = M Q_0 + M' Q_0'$ $J_2 = K_2 = M Q_1 Q_0 + M' Q_1' Q_0'$

State table (excerpt)

Circuit

1. Three JK flip-flops with a common clock.
2. $J_0=K_0=1$.
3. For $FF_1$: an XNOR (or AND-OR) circuit of $M$ and $Q_0$ gives $J_1=K_1$.
4. For $FF_2$: two AND gates $MQ_1Q_0$ and $M'Q_1'Q_0'$ with an OR gate give $J_2=K_2$.

Check. Up, state $011$: $J_1 = Q_0 = 1$, $J_2 = Q_1Q_0 = 1$, so all three toggle and the next state is $100$. Down, state $100$: $J_1=Q_0'=1$ and $J_2=Q_1'Q_0'=1$, so all three toggle, giving $011$.