Digital Logic

Take $F(A,B,C,D) = \sum(1,2,3,4,8)$ with $A$ as the MSB.

(a) Using a decoder. Use a $4 \times 16$ decoder with inputs $A, B, C, D$. Its outputs are the minterms $m_0 \ldots m_{15}$. Since a decoder gives each minterm separately, connect the outputs $m_1, m_2, m_3, m_4, m_8$ to a 5-input OR gate:

$F = m_1 + m_2 + m_3 + m_4 + m_8$

 A B C D --> [ 4 x 16 DECODER ] -- m1, m2, m3, m4, m8 --> [ 5-input OR ] --> F

(b) Using a multiplexer. Use an $8 \times 1$ MUX with $A, B, C$ as the select lines ($S_2S_1S_0$) and $D$ (or its complement, 0 or 1) on the data inputs. Pair the minterms by $ABC$:

So the data inputs are $I_0 = D,\ I_1 = 1,\ I_2 = D',\ I_3 = 0,\ I_4 = D',\ I_5 = I_6 = I_7 = 0$, and the MUX output is $F$.

(c) Using a PLA. First simplify with a K-map. The prime implicants are: $m_1, m_3 \to A'B'D$; $m_2, m_3 \to A'B'C$; $m_4$ alone $\to A'BC'D'$; $m_8$ alone $\to AB'C'D'$. Hence

$F = A'B'D + A'B'C + A'BC'D' + AB'C'D'$

PLA programming table (4 inputs, 4 product terms, 1 output; 1 = true input, 0 = complemented input, - = not connected, 1 in the output column = term connected to the OR gate):

In the PLA diagram, the AND array has four AND gates that receive the inputs $A, B, C, D$ and their complements, with fuses left intact only where the table has 0 or 1. The OR array has one OR gate with all four product-term fuses intact, giving $F$.

Serial and parallel transfer

Serial to parallel conversion. The serial data are fed bit by bit into the serial input of a shift register. After $n$ clock pulses the $n$ bits occupy the $n$ flip-flops, and all the flip-flop outputs $Q_{n-1} \ldots Q_0$ can be read at the same time as the parallel word. Example: serial input stream $1, 0, 1, 1$ shifted into a 4-bit register gives $Q_3Q_2Q_1Q_0 = 1011$ after four pulses. This is a serial-in parallel-out (SIPO) operation.

Parallel to serial conversion. The parallel word is loaded into all the flip-flops at once, using the parallel data inputs and a Load control (for example a multiplexer in front of each D input selecting between parallel data and the previous stage). The control is then switched to shift mode, and on each clock pulse the word moves one place and one bit leaves at the serial output. After $n$ pulses all $n$ bits have been sent. This is a parallel-in serial-out (PISO) operation.

 Parallel in -> [load] -> FF3 -> FF2 -> FF1 -> FF0 -> Serial out   (shift right)
 Serial in  -> FF3 -> FF2 -> FF1 -> FF0 -> parallel outputs Q3 Q2 Q1 Q0

Type of register needed. A shift register: serial-in parallel-out for serial to parallel, and parallel-in serial-out for parallel to serial. A single shift register with parallel load, shift right control and a serial input and output (a universal shift register) can perform both conversions.

Even parity generator. An even parity generator adds a parity bit $P$ to the data so that the total number of 1s in the data plus parity bit is even. So $P = 1$ when the number of 1s in the 4 data bits is odd.

Truth table (data $ABCD$)

Expression. The K-map has a checkerboard pattern (no two 1s adjacent), so no simplification is possible in SOP form, but the function is the exclusive-OR of all the inputs:

$P = \sum(1,2,4,7,8,11,13,14) = A \oplus B \oplus C \oplus D$

Circuit. Three 2-input XOR gates: $A \oplus B$ and $C \oplus D$ in the first level, and their outputs XORed in the second level to give $P$. The transmitted 5-bit word is $A\,B\,C\,D\,P$, which always has an even number of 1s.

 A --\
      XOR --\
 B --/       \
              XOR --> P
 C --\       /
      XOR --/
 D --/

Take the function in variables $x,y,z$ ($x$ is the MSB):

$F(x,y,z)=\Sigma(0,3,5,6,7)$

(a) Using a 3-to-8 decoder. Connect $x,y,z$ to the select inputs $A_2,A_1,A_0$. The decoder produces all minterms $m_0 \ldots m_7$ on its outputs. Since $F$ is the sum of minterms, an OR gate collects the required outputs:

$F=m_0+m_3+m_5+m_6+m_7$

Outputs $D_0, D_3, D_5, D_6, D_7$ go to a 5-input OR gate whose output is $F$ (outputs $D_1, D_2, D_4$ are left unused). Alternatively, $F'=m_1+m_2+m_4$ can be formed with a 3-input OR and inverted.

(b) Using a multiplexer. Use a 4-to-1 MUX with $x,y$ as select lines ($S_1=x$, $S_0=y$) and $z$ as the data variable. Build the implementation table:

Circled (present) minterms: 0, 3, 5, 6, 7. For each column:

• $xy=00$: only $m_0$ present ($z=0$), so $I_0=z'$.
• $xy=01$: only $m_3$ present ($z=1$), so $I_1=z$.
• $xy=10$: only $m_5$ present ($z=1$), so $I_2=z$.
• $xy=11$: both $m_6, m_7$ present, so $I_3=1$.

Connections: $I_0=\bar z$, $I_1=z$, $I_2=z$, $I_3=1$, selects $S_1=x$, $S_0=y$, output $=F$.

(c) Using a PLA. First simplify with a K-map:

Groups: $m_3,m_7$ gives $yz$; $m_5,m_7$ gives $xz$; $m_6,m_7$ gives $xy$; $m_0$ stays alone as $x'y'z'$.

$F=x'y'z'+yz+xz+xy$

The PLA needs 3 inputs ($x,y,z$), 4 product terms and 1 output. AND-plane programming:

In the AND plane, fuses are kept for the literals shown (complemented or true form; "-" means no connection). In the OR plane, all four product terms are connected to the output $F$.

Specification. For inputs $xyz$ from 0 to 3 the output is the input $+ 1$; for inputs 4 to 7 the output is the input $- 1$. Three output bits $ABC$ are enough (the largest output is 6).

Truth table

Simplification

• $A = \sum(3, 5, 6, 7)$. K-map groups $m_3, m_7 = yz$; $m_5, m_7 = xz$; $m_6, m_7 = xy$. So $A = xy + xz + yz$.
• $B = \sum(1, 2, 4, 7)$. No two minterms are adjacent (a checkerboard pattern), so $B = x'y'z + x'yz' + xy'z' + xyz = x \oplus y \oplus z$.
• $C = \sum(0, 2, 4, 6) = z'$.

Circuit. $C$ is just an inverter on $z$. $B$ uses two XOR gates. $A$ is the majority function: three 2-input AND gates feeding a 3-input OR gate.

$A = xy + yz + zx, \qquad B = x \oplus y \oplus z, \qquad C = z'$

$F(P,Q,R,S) = \Sigma(3,4,6,8,9,14)$, with $P$ as the MSB.

(a) Using an 8-to-1 multiplexer

Connect $P, Q, R$ to the select lines $S_2, S_1, S_0$ and express each data input in terms of $S$. Each data line covers a pair of minterms $m_{2i}$ (S = 0) and $m_{2i+1}$ (S = 1):

So $I_0 = I_5 = I_6 = 0$, $I_4 = 1$, $I_1 = S$, and $I_2 = I_3 = I_7 = S'$ (one inverter). Output of the MUX is $F$.

(b) Using a PLA

K-map (rows $PQ$, columns $RS$ in Gray order):

Groups: $m_4, m_6$ gives $P'QS'$; $m_6, m_{14}$ gives $QRS'$; $m_8, m_9$ gives $PQ'R'$; $m_3$ alone gives $P'Q'RS$.

$F = P'QS' + QRS' + PQ'R' + P'Q'RS$

PLA programming table:

The AND plane makes these 4 product terms (with inputs and complements available) and the OR plane connects them to output $F$.

(c) Using a decoder

Use a $4\times16$ decoder with inputs $P, Q, R, S$ whose outputs $D_0 \ldots D_{15}$ are the minterms, and a 6-input OR gate:

$F = D_3 + D_4 + D_6 + D_8 + D_9 + D_{14}$

 P Q R S --> [4x16 decoder] --D3 --\
                             D4 ---\
                             D6 ----\
                             D8 -----> OR --> F
                             D9 ----/
                             D14---/

Design procedure of combinational circuits

A combinational circuit has outputs that depend only on the present inputs. The design steps are:

1. State the problem and decide the number of inputs and outputs.
2. Assign letter symbols to the inputs and outputs.
3. Derive the truth table that defines the required input-output relation.
4. Obtain the simplified Boolean function for each output (K-map or algebra).
5. Draw the logic diagram and verify it.

Design of the given circuit

Inputs $x,y,z$ (binary number $N$), outputs $A,B,C$ ($A$ is the MSB). For $N=0$ to 3 the output is $N+1$; for $N=4$ to 7 the output is $N-1$.

From the table:

$A=\Sigma(3,5,6,7)\qquad B=\Sigma(1,2,4,7)\qquad C=\Sigma(0,2,4,6)$

K-map simplification (rows $x$, columns $yz=00,01,11,10$):

• $A$: the 1s are at $m_3,m_5,m_6,m_7$. Pairs $m_3m_7$ ($yz$), $m_5m_7$ ($xz$), $m_6m_7$ ($xy$) give $A=xy+yz+zx$
• $B$: the 1s are at $m_1,m_2,m_4,m_7$, a checkerboard with no adjacent pairs. This is the odd-parity function: $B=x'y'z+x'yz'+xy'z'+xyz=x\oplus y\oplus z$
• $C$: the 1s are at $m_0,m_2,m_4,m_6$, the whole column $z=0$: $C=z'$

Logic diagram.

• $A$: three 2-input AND gates ($xy$, $yz$, $zx$) feeding one 3-input OR gate.
• $B$: two cascaded XOR gates, $(x\oplus y)\oplus z$.
• $C$: one NOT gate on $z$.

The circuit therefore needs 3 AND, 1 OR, 2 XOR and 1 NOT gate.

1-to-16 demultiplexer. A demultiplexer has one data input $D$, $n$ select lines and $2^n$ outputs. It routes the input to exactly one output, chosen by the select code. For 16 outputs, $n=4$ select lines $S_3S_2S_1S_0$ are needed.

Block diagram.

              +-----------------+
              |                 |--- Y0
              |                 |--- Y1
   D  ------->|                 |--- Y2
              |   1 x 16 DEMUX  |  ...
              |                 |--- Y14
              |                 |--- Y15
              +--+--+--+--+-----+
                 |  |  |  |
                S3 S2 S1 S0

Truth table (output $Y_i$ equals $D$ when $S_3S_2S_1S_0$ equals the binary value of $i$; all other outputs are 0):

Logic circuit. Each output is a 5-input AND gate of the data input and a select combination (using inverters for complemented selects):

$Y_0=D\,\bar S_3\bar S_2\bar S_1\bar S_0,\quad Y_1=D\,\bar S_3\bar S_2\bar S_1 S_0,\quad \ldots,\quad Y_{15}=D\,S_3S_2S_1S_0$

So the circuit has four inverters (for $\bar S_3,\bar S_2,\bar S_1,\bar S_0$) and sixteen 5-input AND gates; the data line $D$ is connected to one input of every AND gate.

Working principle. The four select bits form a binary number from 0 to 15. Only the AND gate whose select pattern matches this number has all its inputs at 1 when $D=1$, so only that output equals $D$; every other AND gate has at least one 0 input, so its output stays 0. For example, with $S_3S_2S_1S_0=1010$ ($=10$), only $Y_{10}$ follows $D$. The circuit is the same as a 4-to-16 decoder with $D$ used as the enable input. It can also be built from a tree of 1-to-2 or 1-to-4 demultiplexers.

Use 8 bits (sign bit plus 7 magnitude bits). Negative numbers are stored in 2's complement.

Representations.

• $+42 = 00101010$
• $+13 = 00001101$
• $-13$: 1's complement of $00001101$ is $11110010$; add 1 to get $11110011$.
• $-42$: 1's complement of $00101010$ is $11010101$; add 1 to get $11010110$.

(a) $(+42)+(-13)$.

  00101010   (+42)
+ 11110011   (-13)
-----------
1 00011101

The carry out of the sign bit is discarded (the carries into and out of the sign bit are both 1, so there is no overflow). Result $=00011101 = 16+8+4+1 = +29$. Check: $42-13=29$.

(b) $(-42)-(-13)$. Subtraction is done by adding the 2's complement of the subtrahend. The 2's complement of $-13$ ($11110011$) is $00001101$ $(+13)$. So

  11010110   (-42)
+ 00001101   (+13)
-----------
  11100011

There is no carry out. The sign bit is 1, so the result is negative. Its magnitude is the 2's complement of $11100011$: invert to $00011100$, add 1 to get $00011101 = 29$. Result $=-29$. Check: $-42+13=-29$.

For a 4-variable function there are $2^4=16$ minterms ($0$ to $15$). The complement $F'$ consists of exactly those minterms that are not in $F$.

$F(A,B,C,D)=\Sigma(0,2,6,11,13,14)$

All minterms: $0,1,2,\ldots,15$. Removing $0,2,6,11,13,14$ leaves $1,3,4,5,7,8,9,10,12,15$. Hence

$F'(A,B,C,D)=\Sigma(1,3,4,5,7,8,9,10,12,15)$

Check: $F$ has $6$ minterms and $F'$ has $10$, and $6+10=16$.

In terms of maxterms, $F=\Pi(1,3,4,5,7,8,9,10,12,15)$, i.e. the minterms of $F'$ are the maxterm numbers of $F$.

$F = wxy + yz + xy'z + x'y$

Expand to minterms (index $=8w+4x+2y+z$):

• $wxy$: $w=x=y=1$, $z$ any, giving $14, 15$
• $yz$: $y=z=1$, giving $3, 7, 11, 15$
• $xy'z$: $x=1,y=0,z=1$, giving $5, 13$
• $x'y$: $x=0,y=1$, giving $2, 3, 6, 7$ and $10, 11$ (with $w=1$)

$F=\Sigma(2,3,5,6,7,10,11,13,14,15)$

K-map (rows $wx$, columns $yz$):

Grouping.

• Octet of the two columns $11$ and $10$ (all $y=1$ cells: $2,3,6,7,10,11,14,15$) gives $y$.
• Quad of cells $5,7,13,15$ (rows $01$ and $11$, columns $01$ and $11$) gives $xz$.

$F = y + xz$

Check: $y=1$ covers 8 minterms, and $xz$ with $y=0$ adds $5$ and $13$, a total of $10$ minterms, matching the original function.

Design. Let the 3-bit input be $ABC$ ($A$ the MSB). The largest input is $7$, and $7^2 = 49 < 64$, so six output bits $B_5B_4B_3B_2B_1B_0$ are enough.

Truth table

Simplification from the minterms

• $B_0 = \sum(1,3,5,7) = C$
• $B_1 = 0$ (a square is always $0$ or $1 \pmod 4$, so this bit is always 0)
• $B_2 = \sum(2,6) = BC'$
• $B_3 = \sum(3,5) = A'BC + AB'C = C(A \oplus B)$
• $B_4 = \sum(4,5,7) = AB' + AC = A(B' + C)$
• $B_5 = \sum(6,7) = AB$

Circuit. $B_0$ is connected directly to $C$ and $B_1$ is tied to logic 0. $B_2$ uses one NOT and one AND gate. $B_3$ uses one XOR and one AND gate. $B_4$ uses one NOT, one OR and one AND gate. $B_5$ uses one AND gate. Only the inputs $A$, $B$, $C$ (and their complements) are needed, so the whole circuit is a small two-level combinational network.

Idea. A $5 \times 32$ decoder has inputs $A_4A_3A_2A_1A_0$ and 32 outputs $D_0 \ldots D_{31}$. The two most significant bits $A_4A_3$ select one of four groups of eight outputs; the three least significant bits $A_2A_1A_0$ select one output inside the group.

• A $2 \times 4$ decoder takes $A_4A_3$. Its four outputs $Y_0, Y_1, Y_2, Y_3$ drive the enable inputs $E$ of the four $3 \times 8$ decoders, so only one of them is active at a time.
• The three lines $A_2A_1A_0$ are connected in parallel to the select inputs of all four $3 \times 8$ decoders.

Block diagram

                     +-----------+
 A4 ---------------->|           |--Y0--> E of DEC-0 (3x8) -> D0  ... D7
 A3 ---------------->| 2 x 4 DEC |--Y1--> E of DEC-1 (3x8) -> D8  ... D15
                     |           |--Y2--> E of DEC-2 (3x8) -> D16 ... D23
                     +-----------+--Y3--> E of DEC-3 (3x8) -> D24 ... D31

 A2 A1 A0 ---------> (common to the select inputs of all four 3x8 decoders)

Working. When $A_4A_3 = 00$, only the first $3 \times 8$ decoder is enabled and gives outputs $D_0$ to $D_7$ according to $A_2A_1A_0$. For $A_4A_3 = 01$, the second decoder gives $D_8$ to $D_{15}$; for $10$ the third gives $D_{16}$ to $D_{23}$; for $11$ the fourth gives $D_{24}$ to $D_{31}$. The disabled decoders keep all their outputs at the inactive level. For example, $A_4A_3A_2A_1A_0 = 10110$ enables decoder 2 and selects its output 6, which is $D_{22}$.

Decimal (BCD) adder. A decimal adder adds two BCD digits and a carry-in and produces a BCD digit and a carry-out. Since each digit is at most 9, the largest sum is $9 + 9 + 1 = 19$.

Method. Add the two BCD digits and the input carry with an ordinary 4-bit binary adder. This gives a binary sum $K\,Z_8Z_4Z_2Z_1$. If the sum is 9 or less, it is already the correct BCD digit. If it is 10 to 19, it is not valid BCD, and adding $0110_2$ (6) corrects it and produces the decimal carry.

Truth table

Correction condition. Correction is needed when the binary sum has produced a carry ($K = 1$, sums 16 to 19) or when the 4-bit result is 10 to 15, i.e. $Z_8 = 1$ together with $Z_4 = 1$ or $Z_2 = 1$:

$C = K + Z_8Z_4 + Z_8Z_2$

When $C = 1$, the number $0110$ is added to $Z_8Z_4Z_2Z_1$ and the carry-out of the digit is $C$.

Diagram

 A (4-bit BCD) --+
 B (4-bit BCD) --+--> [ 4-bit binary adder 1 ] <-- Cin
                          |  K (carry)   Z8 Z4 Z2 Z1
                          |
                 K + Z8.Z4 + Z8.Z2  (AND-OR gates) ---> C = carry-out
                          |
                          +--> 0 C C 0  (= 0110 when C=1, else 0000)
                                        |
 Z8 Z4 Z2 Z1 ------> [ 4-bit binary adder 2 ] ---> S8 S4 S2 S1

The first adder forms the binary sum, the AND-OR logic generates $C$, and the second adder adds $0\,C\,C\,0$ (6 or 0) to give the corrected BCD digit. The carry $C$ is passed to the next decade for multi-digit addition. Example: $8 + 7 = 15 = 01111$; $Z_8Z_4 = 1$, so $C = 1$; $1111 + 0110 = 1\,0101$, and the discarded carry gives the BCD result $1\ 0101$, i.e. 15.

Shift register with parallel load. A shift register is a group of flip-flops connected in cascade so that the binary data stored in them moves one position on each clock pulse. A shift register with parallel load can additionally load all of its flip-flops simultaneously from external parallel inputs, so it can be loaded in parallel and shifted serially.

Structure (4 bits). Each flip-flop $Q_i$ has a $2 \times 1$ multiplexer in front of its D input. The select line is a control input $\text{Shift}/\overline{\text{Load}}$:

• $\text{Shift}/\overline{\text{Load}} = 0$: $D_i = I_i$ (parallel data input), so all four bits are loaded at the next clock edge.
• $\text{Shift}/\overline{\text{Load}} = 1$: $D_i = Q_{i-1}$ (output of the previous stage), and the serial input feeds the first stage, so the data shifts one place right.

 Serial in --> [MUX]->[D FF Q3]-->[MUX]->[D FF Q2]-->[MUX]->[D FF Q1]-->[MUX]->[D FF Q0]--> Serial out
                 ^                  ^                  ^                  ^
                I3                 I2                 I1                 I0      (parallel inputs)
 All MUX select lines = Shift/Load;   all flip-flops share the same clock

Function table

Practical implications

1. It converts parallel data to serial data (load in one clock pulse, then shift out bit by bit) and serial data to parallel data, which is essential in serial communication such as UART and keyboard or modem interfaces.
2. It is the basic building block of the accumulator and arithmetic units in a computer, where shifting left or right multiplies or divides by 2.
3. It can be used as a temporary storage register, a delay line, and to build ring and twisted-ring (Johnson) counters.
4. Because the data are loaded and shifted under control of the same clock, the multiplexers add gate delay in front of every flip-flop. The clock rate is therefore limited by the multiplexer delay plus the flip-flop setup time.
5. Serial transfer needs only one data line but $n$ clock pulses, while parallel transfer needs $n$ lines but one pulse, so the register lets the designer trade wiring against speed.

Master-slave J-K flip-flop. A plain level-triggered J-K latch suffers from the race-around condition: when $J = K = 1$ and the clock stays high longer than the propagation delay, the output toggles repeatedly during one clock pulse. The master-slave arrangement removes this problem.

Construction. It consists of two clocked J-K (or SR) latches in cascade:

• the first is the master, the second is the slave;
• the master is enabled by the clock $CP$, the slave by its complement $\overline{CP}$ (through an inverter);
• the outputs $Q$ and $Q'$ of the slave are fed back to the master's inputs, giving $S = J\,Q'$ and $R = K\,Q$.

 J --+--[AND]--+                          +-----------+
 CP -+--[AND]--+--> MASTER latch --Qm,Qm'-->  SLAVE    +--> Q
 K --+--[AND]--+     (enabled when CP=1)   |  (enabled |--> Q'
      ^   ^                               |  when CP=0)|
      |   +-------- feedback Q, Q' -------+-----------+

Working

1. When $CP = 1$, the master is enabled and takes up the state decided by $J$, $K$ and the fed-back $Q$, $Q'$. The slave is disabled, so the output $Q$ does not change.
2. When $CP$ falls to 0, the master is disabled (it holds the value it captured) and the slave is enabled. The slave copies the master's state, so the output changes only at the falling edge of the clock.
3. Because the output only changes after the master is isolated, the changed $Q$ cannot reach the master input while the master is active, so there is no race-around.

Truth table

Characteristic equation: $Q(t+1) = JQ' + K'Q$.

The master-slave J-K flip-flop therefore acts as a negative-edge triggered flip-flop: the output transition occurs at the end (falling edge) of the clock pulse, using the input values present during the pulse, and it can be used safely as a toggle element in counters.

(a) State diagram. A state diagram is the graphical representation of a sequential circuit. Each state (the contents of the flip-flops) is drawn as a circle, and a directed arrow between circles shows a transition. The arrow is labelled with the input that causes the transition and, for a Mealy machine, the output as well (input/output); in a Moore machine the output is written inside the circle. For example, a T flip-flop has two states, 0 and 1. With $T = 1$, the arrow goes from 0 to 1 and from 1 to 0; with $T = 0$, a loop arrow keeps the state. State diagrams are the first step in sequential design: from the diagram the state table is built, then the flip-flop input equations are found with K-maps.

(b) De Morgan's theorem. It states two rules relating AND, OR and complement:

$(A + B)' = A' \cdot B' \qquad (A \cdot B)' = A' + B'$

The complement of a sum is the product of the complements, and the complement of a product is the sum of the complements. It extends to any number of variables: $(A + B + C)' = A'B'C'$. Proof for the first rule: if $A = B = 0$ both sides are 1; in every other case the left side is 0 and the right side contains a 0 factor, so is 0. The theorem is used to convert an AND-OR network into NAND-NAND or an OR-AND network into NOR-NOR form, and to find the complement of a function.

(c) TTL. Transistor-Transistor Logic is a bipolar logic family in which the input stage uses a multiple-emitter transistor and the output stage is a totem-pole (a pull-up transistor on top of a pull-down transistor). The 74xx series is the standard TTL series, with a supply of $+5\text{ V}$, logic-0 below $0.8\text{ V}$ and logic-1 above $2.0\text{ V}$ at the input. Typical figures: propagation delay about $10\text{ ns}$ and power dissipation about $10\text{ mW}$ per gate for standard TTL, fan-out 10. Variants are Schottky (74S), low-power Schottky (74LS), advanced versions, and open-collector and tri-state outputs. TTL is fast and cheap but dissipates more power than CMOS.

Step 1: simplify each output (inputs $X, Y, Z$ with $X$ the MSB).

• $A = \sum(1,2,4,6) = X'Y'Z + XZ' + YZ'$
• $B = \sum(1,3,6,7) = X'Z + XY$
• $C = \sum(1,2,4,6,7) = X'Y'Z + XZ' + YZ' + XY$
• $D = \sum(1,2,3,5,7) = Z + X'Y$

Step 2: PAL programming table. In a PAL, the AND array is programmable but each OR gate is fixed to its own set of product terms, so terms cannot be shared between outputs. Here at most 4 terms per output are needed, so a PAL with four product terms per OR gate is enough. In the table, 1 means the true input is connected, 0 means the complemented input is connected, and - means the input is not connected (both fuses blown).

Step 3: fuse map for the PAL diagram. Every AND gate has six input lines $X, X', Y, Y', Z, Z'$, each with a fuse. A fuse is left intact (marked ×) where the table requires the line, and all other fuses of that gate are blown. Unused AND gates in an OR gate keep all fuses intact (output 0).

The remaining fuses (the ones marked "blown") are the ones to be burnt out in the PAL diagram; the intact fuses form the four product-term groups feeding the four fixed OR gates $A, B, C, D$.

Check, e.g. $XYZ = 110$: term 2 ($XZ'$) gives $A = 1$; term 5 gives $B = 1$; terms 7, 9 give $C = 1$; $D$ terms are both 0, so $D = 0$. This matches the row $1\,1\,1\,0$.